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8 Failure Modes, Reliability Issues, and Case Studies 228
) l6 O. F/ t/ B8.1 Introduction 228) o# s9 |, b b8 V! D. y2 Z
8.2 Failure Mode Analysis 229
0 T8 `/ @8 E9 Q% G' ?" \8.3 Reliability and Performance Considerations 238, f* O0 o" _5 z: t5 F
8.4 Advanced CMOS Input Protection 239! t' F2 M' L( i2 n4 c
8.5 Optimizing the Input Protection Scheme 242
4 X6 G# }) Z2 |$ C# v8.6 Designs for Special Applications 249* Q5 a% q- Z" I) g( {9 x
8.7 Process Effects on Input Protection Design 2538 Z4 J8 ^% F3 E- i3 @
8.8 Total IC Chip Protection 2556 X& o5 a& I1 `0 T3 u- e8 u
8.9 Power Bus Protection 256
8 F( a6 T7 z1 p8.10 Internal Chip ESD Damage 258/ O/ z$ ?' w! F, f8 V, q% [+ ^
8.11 Stress Dependent ESD Behavior 263
" Q9 ]1 h2 I# R3 l6 ~8.12 Failure Mode Case Studies 2678 s1 O* P! O/ B$ S: Z3 `8 j
8.13 Summary 271/ T( k% y8 i6 T3 {1 Z- A% p
Bibliography 272! w+ @0 x9 G% p- X8 _
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