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8 Failure Modes, Reliability Issues, and Case Studies 228
7 r$ d6 x8 Q* L* _8.1 Introduction 2287 {. D$ X# T |+ }" P; Z
8.2 Failure Mode Analysis 229
% r7 g& O: T8 [7 {8.3 Reliability and Performance Considerations 238
b$ B/ v+ T# G! y- b" `! l1 O8.4 Advanced CMOS Input Protection 239) t5 C; J7 z& g) d
8.5 Optimizing the Input Protection Scheme 2428 H7 M0 j, v6 G8 m6 P$ `
8.6 Designs for Special Applications 249
c, s5 Y; F- z1 J; ~8 o$ K8.7 Process Effects on Input Protection Design 253
* z8 p% s: L* @- ]" h% D8.8 Total IC Chip Protection 255& ^+ O; i& o* L5 G1 J( Z9 o5 K
8.9 Power Bus Protection 256
( e5 C' \$ ]2 ~8.10 Internal Chip ESD Damage 2588 O& ?% N* ~6 @' Q
8.11 Stress Dependent ESD Behavior 263
% V6 z: Z* t7 |0 |; I }0 f& Q8.12 Failure Mode Case Studies 267
7 {9 p2 t2 N% G D" A- W8.13 Summary 271* Y8 ]- R; O! `( g. A
Bibliography 272
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