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Startpoint: U_RST/nResetUSB_reg
' p9 E( ~2 c/ u) @: s (falling edge-triggered flip-flop clocked by CLK48)
, v9 x: E$ N, k: o4 y# h. { Endpoint: u_FUSB/FUS/BIF/PS/q_reg_2_7 Q0 ]/ k* ^) \/ W# ^# X
(rising edge-triggered flip-flop clocked by CLK48)0 a3 Q- k* ]6 r9 f3 P% j, F
Path Group: CLK48- \2 J; C5 D: j$ X' M) u2 ]6 B
Path Type: max
/ ~- m* N! |% o/ K% [# d7 `* D* p$ X) o$ |
Point Incr Path' _- w0 i1 v, P! | n9 c
--------------------------------------------------------------------------! `0 b: D5 N. A- |6 B
clock CLK48 (fall edge) 9.00 9.00; n, c% N& ^0 ]
clock network delay (ideal) 2.00 11.00" t' S- M2 ~; _6 b q0 U
U_RST/nResetUSB_reg/CKB (DBFRBN) 0.00 11.00 f* _8 ^1 o/ ^' x6 g" ~0 H/ d
U_RST/nResetUSB_reg/Q (DBFRBN) 1.27 12.27 r2 p+ M" }3 ~# |$ v N
U_RST/nResetUSB (ResetGen) 0.00 12.27 r
' B8 F, O4 F; f" ]- f* s u_FUSB/RESETN (kFUS100_2m) 0.00 12.27 r
- g8 K8 X3 W7 Q' H. m u_FUSB/U132/O (BUF1) 0.32 12.59 r! g* p; _6 ^" E- z8 E5 k! _7 b
u_FUSB/FUS/RESET_INN (LFUS) 0.00 12.59 r
6 ~0 A3 J, T5 H u_FUSB/FUS/BIF/RESET_INN (LUSBIF) 0.00 12.59 r
' J% k4 `+ R; f' w' \: B% V u_FUSB/FUS/BIF/U42/O (BUF1) 0.33 12.92 r
) [+ G& x. z v: F8 z% H u_FUSB/FUS/BIF/U49/O (AN2) 0.44 13.36 r
7 P4 D* V! S* k/ B' G6 K u_FUSB/FUS/BIF/U50/O (AN2) 0.64 14.00 r
% ~ k6 x! p9 I, R- l: A u_FUSB/FUS/BIF/RESETN (LUSBIF) 0.00 14.00 r( i" t9 w5 I; j) ]1 ^# ?
u_FUSB/FUS/U44/O (BUF1) 0.69 14.69 r4 O* I% q7 F' B5 f' h
u_FUSB/FUS/LDSCR/RESETN (LDSCR) 0.00 14.69 r' g7 X) i/ }& g5 x8 D. d! m! P
u_FUSB/FUS/LDSCR/U85/O (INV1) 0.22 14.91 f7 m7 D# `" g1 R) ?' \* d/ U2 a$ Z% x
u_FUSB/FUS/LDSCR/U222/O (NR2) 0.46 15.37 r |1 {; r: J3 n5 [9 f$ C2 a! T
u_FUSB/FUS/LDSCR/U8/O (AO12) 0.46 15.83 r& V6 k- ~/ I( l( L
u_FUSB/FUS/LDSCR/U10/O (AN3) 0.50 16.33 r8 s, z1 Q9 L) g. k9 c
u_FUSB/FUS/LDSCR/U7/O (AO222) 0.51 16.84 r
' C2 p0 ~4 |/ _ u_FUSB/FUS/LDSCR/U206/O (AN2) 0.36 17.21 r
) T8 ~& ^" ? x7 x1 L: P( x u_FUSB/FUS/LDSCR/epC/InterruptRD (LDSC_EPC) 0.00 17.21 r
% Q( s* A4 |- C u_FUSB/FUS/LDSCR/epC/U87/O (INV1) 0.12 17.33 f3 ^, K. T O7 X4 g C) V. \$ F
u_FUSB/FUS/LDSCR/epC/U83/O (OR3B2) 0.34 17.66 f' O7 _. e( ?3 V) |
u_FUSB/FUS/LDSCR/epC/U82/O (NR2) 0.38 18.04 r
; b! ?1 j+ U: X! J, J u_FUSB/FUS/LDSCR/epC/U63/O (AO112) 0.50 18.54 r
# f' Z- O. g7 F4 L4 b& O1 k9 X5 \3 F% P' \ u_FUSB/FUS/LDSCR/epC/D_epC[2] (LDSC_EPC) 0.00 18.54 r
$ p2 U0 g* Y0 B9 k u_FUSB/FUS/LDSCR/U158/O (ND2) 0.12 18.66 f7 U! @" F# D: n p
u_FUSB/FUS/LDSCR/U156/O (OR3B2) 0.19 18.84 r; q% O5 }5 M: \" E/ \0 c9 z* q
u_FUSB/FUS/LDSCR/DD[2] (LDSCR) 0.00 18.84 r
. a/ ~' a4 O1 Q! d u_FUSB/FUS/MIS/DD[2] (LMISC) 0.00 18.84 r% ^- {; b( J; G
u_FUSB/FUS/MIS/U47/O (AO222) 0.36 19.21 r
) b- m9 F; n1 }3 E- Q$ b" m u_FUSB/FUS/MIS/U45/O (OR2) 0.26 19.47 r2 M$ C+ g% e3 ?' [5 f
u_FUSB/FUS/MIS/Q[2] (LMISC) 0.00 19.47 r
8 z a3 H# E6 i/ i4 T u_FUSB/FUS/BIF/DOUT[2] (LUSBIF) 0.00 19.47 r& j! a4 F& c6 e5 `6 E3 F
u_FUSB/FUS/BIF/U29/O (AO222) 0.32 19.79 r+ e, ?9 b! }& M
u_FUSB/FUS/BIF/PS/DIN[2] (LP2S) 0.00 19.79 r
3 H% X; l' G( [/ u8 N: y u_FUSB/FUS/BIF/PS/U6/O (AO222) 0.33 20.11 r
! ^$ F% r% g# Q/ l u_FUSB/FUS/BIF/PS/q_reg_2_/D (QDFFN) 0.00 20.11 r
\0 a F. j; M data arrival time 20.11
" m& D2 g) }5 y: N0 ? M1 p
& y! |0 s" @2 l! J clock CLK48 (rise edge) 18.00 18.004 a, p$ ?9 H* M, }3 d
clock network delay (ideal) 2.00 20.00
& u# h c# n y8 G+ i9 i clock uncertainty -0.50 19.50
) F, Y/ A$ o% j* g% {6 O u_FUSB/FUS/BIF/PS/q_reg_2_/CK (QDFFN) 0.00 19.50 r
0 R/ i1 U5 N. \0 T, D; F library setup time -0.25 19.25% G0 j k# c9 p$ K/ X
data required time 19.25- o/ c) ~5 @ L; l( c) Y4 G
--------------------------------------------------------------------------
5 w! C2 e2 I S' L$ ~9 T data required time 19.25" U, T2 U; t# j* {7 ?/ Q
data arrival time -20.11/ R/ g5 g2 r- a9 c1 P
--------------------------------------------------------------------------& q% O2 t% O, d! q" i. Z& y$ ~4 m
slack (VIOLATED) -0.861 a5 z; J; P) j( P# Z
0 r% b8 Z/ u& z% Y# q
- r; S* q" @: x E( `請問該如何調整使他met呢?? |
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發表於 2007-12-24 09:53:47
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