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我在之前的公司有lay過double guard rings,內圍是用PTHIN guard rings,外圍是用
! F2 Z. T7 w. ?2 \. ^& oNwell+NTHIN(甜甜圈結構).主要就是用來防止noise,那時是圍在Oscillator外圍.
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Dummy的話,不知道你指的是那部份?? 引述一篇paper " SmartExtract:Accurate Capacitance
1 h/ B W* t z( `2 BExtraction for SOC", 這裡提到的dummy是指layout完成後,在每層layer空曠處,補上同一layer 3 w/ \0 f4 D0 q9 a- `+ F1 x
dummy, 為的是在CMP process時,有較佳的均勻性:
, F2 A, y) m& ?( mDummy(or fill) metal is introduced in the interconnect process flow to enable uniform5 k# F G6 {5 U5 Z3 Q* q
thickness control in the CMP process. Dummy metal needs to be treated as floating metal
2 d% k% V3 d8 A* E' nunless it is intentionally connected to a constant potential. Floating dummy metal
8 t3 [( d& I, oessentially acts as a capacitance divider.! {6 I; e% N, R# ^# W/ e
另外有一種dummy, 之前我在做analog layout時,會在需做match的mos旁,故意lay半顆或整顆
& h6 r/ B. _9 }; Y% `mos,除了你寫的那些原因,我想是因為實體mos的邊緣不見得是像layout般的四方形(what you draw is not what you get),可能是梯形或不規則多邊形,製程上很難做到如此完美,所以為了確保
M- \! q+ m9 @主要的mos的完整性及對稱性,在mos旁再多加dummy mos(不要讓主要mos成為最邊緣的部
' U! S$ T1 `: S$ y4 x份).以上是我自己的想法,歡迎各位先進指教 |
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