時間
9 E2 {. }( E3 n | 活動內容 / I0 G) i. q, P) d9 `
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1:00-1:30
7 z1 D2 {& y0 `0 P | Registration
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1:30-1:35 " r8 g5 |* D+ R8 a1 p5 C6 m- Z
| Introduction: Agenda, who's here,
3 U. R/ ] i- J# o1 F! Pwhat do we do?
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1:35-2:05
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Note: Why prototype?3 z4 O% U/ ?' c! A5 G
ASIC Verification Options$ [7 }; u) P% \) G. o3 U3 L
| Ashok Kulkarni,Technical
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2:05-2:50 . B& |+ u! k6 ]
| V5 for ASIC Prototype- y9 R) N2 d) f/ Z5 A
| Simon Ho, Corporate Solution marketing Manager, Xilinx' [5 a7 b, W: A4 R" }0 K1 M0 o: n" j
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2:50-3:10 0 D/ g% [$ k! m# u* T- U
| Break
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3:10-3:55 * ~/ C7 b/ h$ g0 y: h
| Creating a platform around you FPGA(s) ) _6 F$ a% V" I Y, f; N7 \% u, {
| Ashok Kulkarni,Technical
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3:55-4:25 0 Z6 l+ J+ n; R+ H2 x( X
| Faster FPGA Implementation
: I1 c5 p1 H. z' { | Simon Ho, Corporate Solution marketing Manager, Xilinx
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4:25-5:00 % ]0 B' ?& j: W6 W3 U4 m2 ]4 B
| Making the ASIC design ready for FPGA - HAPS live flow demo, G" E. f2 `( v
| Freddy Lin, ASIC Verification Specialist, Synplicity Taiwan
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5:00-5:30
' B1 i3 P; Q, H6 M2 f9 m$ n# T7 B | Q&A, Lucky Draw and Wrap-up
/ P& ~6 b$ g. Y) E | All
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