You must be sure that, 5 h: G7 L5 p; I! y3 R& ]; m# l& i' H
1. your design output meets standard SVGA HSYNC/VYNC timing' Z" A* f4 _5 K$ _
2. You must also set constraint on the ISE project, and check the timing report after " O% _. V- j, B1 {0 R1 _ the P&R is done. (also called STA timing report)9 A; `6 b" I7 O3 ^7 W
3. Sometimes, you must check the board, and I/O SSO issue(signal integrity....)