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Design and Analysis of Technology Errors5 i) f- o6 @9 { k# L
for CMOS Poly-silicon Capacitor9 ]7 e/ _+ |, ?8 L
ZHUZhang-ming ,YANGYin-tang , ZHANGChun-peng , FUXiao-dong
# Q/ ~2 ^! K) d& W* R: I9 V0 `(Microelectronics Institute ,XidianUniversity,Xi’an 710071 , China)3 W, ~- w+ A" X# F
Abstract : The technology errors of CMOS poly-silicon capacitor are analyzed .The effect of various errors introduced
+ A3 v1 a! e) c; @3 t5 F" P" Cduring fabrication on CMOS poly-silicon capacitor is discussed .Based on the improved design of unit-capacitors , the
" s3 F! F+ K% ~% j, F* Wcommon-centroid floorplan of poly-silicon capacitor is presented . On the proposed capacitor design way , the CMOS* V& L6 r7 Z: @6 q- J: h/ t5 K: A
switch-capacitor bandpass filters is implemented using 0.6μmCMOSDPDMprocess .Themeasured results of filters show
. H+ M# N$ x9 a1 j+ D" o9 o$ B; Mthat the proposed capacitor designway can be used to design high accuracy capacitors ,and applied to the design of submicro
3 u& H ~: _& G# }3 e/ ^. qand deep sub-micro analog integrated circuit ." S" v9 S E' v' ~7 f; [
5 d" r* U6 Z: U) G# s1 q回覆後 可以下載PDF附件 權限10 & 3RDB
* X5 P" s% ~1 I% D! r, M( t2 `' g+ [5 I9 C1 K# Y% ~2 N2 V
4 K% N8 s# }" E( a0 s$ [0 w[ 本帖最後由 sjhor 於 2007-5-17 10:37 PM 編輯 ] |
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