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Design and Analysis of Technology Errors
3 E3 I9 n" c! B( Jfor CMOS Poly-silicon Capacitor
) {4 A# L# l! Y# GZHUZhang-ming ,YANGYin-tang , ZHANGChun-peng , FUXiao-dong# d X7 i# s0 Y
(Microelectronics Institute ,XidianUniversity,Xi’an 710071 , China)
# b% h1 a) I2 h$ `# I/ LAbstract : The technology errors of CMOS poly-silicon capacitor are analyzed .The effect of various errors introduced
[7 s/ f' s M/ L% b0 C' \# E/ lduring fabrication on CMOS poly-silicon capacitor is discussed .Based on the improved design of unit-capacitors , the
* f) k. Q# S9 w Mcommon-centroid floorplan of poly-silicon capacitor is presented . On the proposed capacitor design way , the CMOS' ~5 C0 c; s/ T+ I, l0 e' L3 R! [
switch-capacitor bandpass filters is implemented using 0.6μmCMOSDPDMprocess .Themeasured results of filters show. V0 O( `0 p! Z1 o# R2 a3 W
that the proposed capacitor designway can be used to design high accuracy capacitors ,and applied to the design of submicro
8 Q" M% e7 ^& _/ w# z, n/ r5 h+ nand deep sub-micro analog integrated circuit .
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9 {5 ]6 h* b% v6 H( d# K[ 本帖最後由 sjhor 於 2007-5-17 10:37 PM 編輯 ] |
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