Calibration techniques in nyquist AD converters

cnasic

Table of contents
9 I+ H$ ~' [2 B, AList of abbreviations
$ T' F/ n& s7 _4 G3 vList of symbols
Preface
1 Introduction 1
1.1 A/Dconversion systems . . . . . . . . . . . . . . . . . . . . . . 1
3 Q5 _! }& Y, J9 t1.2 Motivation and objectives . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Layout of the book . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Accuracy, speed and power relation 7
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 IC-technology accuracy limitations . . . . . . . . . . . . . . . . . 8
$ T9 K0 a  H& H" G- G: f) m2.2.1 Process mismatch . . . . . . . . . . . . . . . . . . . . . . 8
2 X0 j# ?2 y2 |8 G. R8 M2.2.2
2.2.3 Matching versus noise requirements . . . . . . . . . . . . 11
2 m8 h* H7 v( Y- Q% j2.3 Speed and power . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Maximumspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 . . . . . . . . . . . . . . . . . . . . . 15
8 t% Q9 z# P( l4 C2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 A/D converter architecture comparison 21
5 w9 U+ ~1 Z3 H, b3 Y3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
0 z+ G- z, k. `$ g& P. f- h3.2 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
/ B$ E3 K- ]; @! Z3.2.1 Fullflash . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . 26
8 K- x" x5 m2 i7 W1 L) c3.2.3 Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Folding and interpolation . . . . . . . . . . . . . . . . . . . . . . 33
' M- N5 q+ l2 T, w" S, m+ ^0 W3.4 Two-step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Thermal noise . . . . . . . . . . . . . . . . . . . . . . . 10
/ l. l  h2 [  Y0 V2 B5 j# xCMOS technology trends
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xiii
7 n8 f+ t7 z1 X) D, p- m9 Ixvii
Table of contents
3.5 Pipe-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.6 Successive approximation . . . . . . . . . . . . . . . . . . . . . . 54
3.7 Theoretical power consumption comparison . . . . . . . . . . . . 56
3.7.1 Figure-of-Merit (FoM) . . . . . . . . . . . . . . . . . . . 57
5 E! k/ V; n# e( q# f3.7.2 Architecture comparison as a function of the resolution . . 57
3.7.3 Architecture comparison as a function of the sampling speed 65
3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4 Enhancement techniques for two-step A/D converters 67
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.2 Error sources ina two-step architecture . . . . . . . . . . . . . . 67
4.3 Residue gain in two-stepA/Dconverters . . . . . . . . . . . . . . 69
, o. _1 c8 Y7 W7 D% _) S0 K4.3.1 Single-residue signal processing . . . . . . . . . . . . . . 69
4.3.2 Dual-residue signal processing . . . . . . . . . . . . . . . 71
4.3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4 Offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 75
! g+ v/ a6 s5 Z( W2 s  A1 c" E4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4.2 Calibration overview . . . . . . . . . . . . . . . . . . . . 75
4.4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 82
, v) L; R+ S( u# t* E% z4.5 Mixed-signal chopping and calibration . . . . . . . . . . . . . . . 83
4.5.1 Residue amplifier offset chopping . . . . . . . . . . . . . 83
$ Y- Z. [4 C) t6 _& J4.5.2 Offset extraction fromdigital output . . . . . . . . . . . . 84
' ?# W2 I0 K1 N  r& G& R4.5.3 Pseudo random chopping . . . . . . . . . . . . . . . . . . 88
' Z( H4 O( k, F+ k4.5.4 Offset extraction and analog compensation . . . . . . . . 91
4.5.5 Offset extraction in a dual-residue two-step converter . . . 93
9 s- N. r" o: T% o7 y: D& r7 _4.5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 102
! T- R$ i$ d3 [5 A 10-bit two-step ADC with analog online calibration 103
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4 B1 O. {. u2 e( j" \' Y5.2
5.2.1 Coarse quantizer accuracy . . . . . . . . . . . . . . . . . 106
" h' Z8 p! i' F7 f7 d5 G- U5.2.2 D/A converter and subtractor accuracy . . . . . . . . . . . 107
4 _! D& f9 W6 @: |; Y5.2.3 Coarse andfineA/Dconverter references . . . . . . . . . 108
5.2.4 Amplifier gain and offset accuracy . . . . . . . . . . . . . 109
* N0 \' t" R, k# p$ U' _8 `5.3 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
0 C" p4 M: Y( r% d5.3.1 Track-and-hold circuit . . . . . . . . . . . . . . . . . . . 111
5.3.2 CoarseA/D,D/Aconverter and subtractor . . . . . . . . . 111
5.3.3 Coarse ladder requirements . . . . . . . . . . . . . . . . . 112
5.3.4 Offset compensated residue amplifier . . . . . . . . . . . 113
1 V$ L3 \+ ?; |2 p2 j1 J5.3.5 FineA/Dconverter . . . . . . . . . . . . . . . . . . . . . 114
5.3.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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Two-Steparchitecture . . . . . . . . . . . . . . . . . . . . . . . 105
- ^- X4 I# ?2 o/ ^: _4 UTable of contents
7 ^/ d/ C5 `7 m8 {3 H1 f$ i5.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . 117
5.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
. d+ u& p  L! @5 A' g8 S5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
. r' \# o; ~  q- @" s$ v6 A 12-bit two-step ADC with mixed-signal chopping and calibration 123
9 [: e7 I& I3 V4 ^3 z: c7 A low-power 16-bit three-step ADC for imaging applications 149

xp212125o

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tuza2000

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