Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

cnasic

Contents
List of Tables
List of Figures
Symbols and Abbreviations
& {: _$ j) w9 S7 cPhysical
; l4 |# I) W& }! O3 y& K- W1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 v7 F; J( o  f- R% F  n1.2 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
7 u, K2 C. C4 w/ t. j4 {* Z2 ADCs in Nanometer CMOS Technologies 3
% t$ S7 m4 @, j: ?3 g2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
) @0 X: a* s3 ~; y" ]0 \2.2 Scaling-Down of CMOS Technologies . . . . . . . . . . . . . . . . . 3
# T# U+ U( @5 ]  V+ E: R2 K' }2.2.1 Driving Force of the CMOS Scaling-Down . . . . . . . . . . 4
2 S5 P3 ^3 Y! Q$ C6 I2.2.2 Moving into Nanometer CMOS Technologies . . . . . . . . . 5
5 s0 n; M" Z6 b/ I/ n, E2.3 Impact of Moving into Nanometer CMOS to Analog Circuits . . . . . 6
2.3.1 Decreased Supply Voltage . . . . . . . . . . . . . . . . . . . 6
2.3.2 Impact on Transistor Intrinsic Gain . . . . . . . . . . . . . . 7
2.3.3 Impact on Device Matching . . . . . . . . . . . . . . . . . . 9
2.3.4 Impact on Device Noise . . . . . . . . . . . . . . . . . . . . 10
% m- p* a1 F7 f1 U2.4 ADCs in Nanometer CMOS . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1 Decreased Signal Swing . . . . . . . . . . . . . . . . . . . . 13
, ^* B" }+ q1 B6 n8 @& b8 K2.4.2 Degraded Transistor Characteristics . . . . . . . . . . . . . . 13
2.4.3 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
+ z5 \$ g& J3 ^9 zvii
. [7 i) s3 A: j8 L2.4.4 Switch Driving . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.5 Improved Device Matching . . . . . . . . . . . . . . . . . . . 17
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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
0 t6 l- L: j) s( x. U6 XDefinitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
; l; t9 r/ K$ ZCONTENTS
2.4.6 Digital Circuits Advantages . . . . . . . . . . . . . . . . . . 17
- A; M7 n7 k5 F$ n' @+ D2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Principle of - ADC 19
& s. u) ~5 q9 ]+ o+ F3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
/ ]* W2 _' V: e" `3.2 Basic Analog to Digital Conversion . . . . . . . . . . . . . . . . . . 19
3.3 Oversampling and Noise Shaping . . . . . . . . . . . . . . . . . . . 24
- M+ L) ?( I- o4 C" u3.3.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . 25
( V( W; o. b7 K  @% d$ b; Y5 y3.3.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.3 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.4 Performance Metrics for the - ADC . . . . . . . . . . . . 31
3.4 Traditional - ADC Topology . . . . . . . . . . . . . . . . . . . . 33
3.4.1 Single-Loop Single-Bit - Modulators . . . . . . . . . . . 33
3.4.2 Single-Loop Multibit - Modulators . . . . . . . . . . . . 37
" Y' i( T: z& y3.4.3 Cascaded - Modulators . . . . . . . . . . . . . . . . . . 39
% J/ u, h/ O/ r, ]+ S$ u- I) t8 A3 f4 q3.4.4 Performance Comparison of Traditional - Topologies . . 46
, m0 t2 |+ P$ b; S! I3 `3 L3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: Circuit
; y7 g: K; d1 H$ eLevel Approach 47
& O9 ~% Q  m: f7 k% ^8 z# m4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
  ~7 ^' F: b' _: i; A- m4.2 Low-Voltage Low-Power OTA Design . . . . . . . . . . . . . . . . . 48
4.2.1 Gain Enhanced Current Mirror OTA Design . . . . . . . . . . 49
4.2.2 A Test Gain-Enhanced Current Mirror OTA . . . . . . . . . . 53
; m/ E, u* M/ n# Y4.2.3 Implementation and Measurement Results . . . . . . . . . . . 54
- Y6 L0 b1 d; e! g4.2.4 Two-Stage OTA Design . . . . . . . . . . . . . . . . . . . . 55
7 x# l7 G4 _) V" p4.3 Low-Voltage Low-Power - ADC Design . . . . . . . . . . . . . . 66
  P. W1 W: ^1 d* r" N1 u4 n9 P0 |+ c4.3.1 Impact of Circuit Nonidealities to - ADC Performance . . 66
4.3.2 Modulator Topology Selection . . . . . . . . . . . . . . . . . 67
4.3.3 OTA Topology Selection . . . . . . . . . . . . . . . . . . . . 69
" h' m8 f/ `6 |4 ]2 ?1 b. f4.3.4 Transistor Biasing . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.5 Scaling of Integrators . . . . . . . . . . . . . . . . . . . . . . 75
9 l. i0 F! K& g& {3 l; _# _4.4 A 1-V 140-μW- Modulator in 90-nm CMOS . . . . . . . . . . . 76
, e' ^  m! @6 B  X5 R4.4.1 Building Block Circuits Design . . . . . . . . . . . . . . . . 76
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5 R. `+ j; s# r) `0 M4 E, {; }( d6 o4.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 80
! y4 B( a$ g  Q2 M" Q4.4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 82
2 k! u% y" j% E' l% f( l4.5 Measurements on PSRR and Low-Frequency Noise Floor . . . . . . . 87
4.5.1 Introduction of PSRR . . . . . . . . . . . . . . . . . . . . . . 87
  ?, ], h% m* Y7 Y  G# A4.5.2 PSRR Measurement Setup . . . . . . . . . . . . . . . . . . . 88
% G" w- Q5 h8 ^9 n0 B4.5.3 PSRR Measurement Results . . . . . . . . . . . . . . . . . . 88
4.5.4 Measurement on Low-Frequency Noise Floor . . . . . . . . . 95
4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: System
CONTENTS ix
CONTENTS
6 Conclusions 149
Bibliography 151
) ]9 K6 `  `) P7 @* g% kIndex 157

scan7510

看不太懂
: s! Z: Q0 g% L( v" O可能還沒學過吧
現在只能單純推一下
謝大大分享

deltachen

謝謝大大的分享~知識因分享而壯大！

jjam

感覺是非常實用的內容
感謝大大的分享~~
希望能對SDM有所認識與了解