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LOAD SDC FILE時
7 g% _0 d; }5 l0 OAstro 訊息) @* K- X# s- E; R7 x/ u0 B( b. {
---------------------------------------------------------------------------7 n+ k |# Y% ]% n' U+ Y
Info: starting Tcl processing/ G, X( M$ M3 M8 t" D+ p8 x( y
Info: building design object name tables & _/ @8 i5 c1 o" y+ ^
Warning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)
* ^+ \7 f& k0 [. AWarning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)
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+ i. G) J* `2 ^SDC FILE
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- U$ G: V3 N' qset_multicycle_path 9 -through [list [get_pins \
: ] i1 M) u7 B8 f2 G" z{TOP/test/mul/A[26]}] [get_pins \8 u- ^6 M8 }/ b; ?
{TOP/test/mul/A[25]}] [get_pins \
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+ w+ r4 m3 G4 ~7 B; t" i
% c/ N# q( N# y-----------------------------------------------------------------------------
+ A. t+ @2 L" r2 t- s7 `Verilog File
% T# J* v5 i" |8 I
R: ~( Z. p- A3 v, m" j0 e uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(
+ d, b" D* z8 i; ?1 s icwAeYfNum[18:0]), .C(ae_avg) ); |
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