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LOAD SDC FILE時- h/ q# S% Z' a* N+ q3 E
Astro 訊息
) u- |% e3 Y4 d- i---------------------------------------------------------------------------# a2 I5 P! L% K
Info: starting Tcl processing
' Z9 M" N5 ]( k- A5 ]$ G+ Z4 Q# }% RInfo: building design object name tables & U7 H# n$ k; C8 f9 y9 |1 U
Warning: No pins matched 'TOP/test/mul/A[26]' (SEL-004). n4 q. }+ Y2 _8 [
Warning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)
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/ i& U- F) q2 \* F& f9 @* Q6 p----------------------------------------------------------------------------: H; e: w7 ]9 W" W/ i$ Z3 C
SDC FILE2 g X, ]# n0 A7 ?
2 e9 |: L; V1 U7 p! \
set_multicycle_path 9 -through [list [get_pins \! R+ t4 I$ t: h! x8 m$ R; X
{TOP/test/mul/A[26]}] [get_pins \8 G7 V3 ?& U/ S
{TOP/test/mul/A[25]}] [get_pins \
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8 u/ d0 F1 ^- X
. q5 W3 _2 N/ N- j. E-----------------------------------------------------------------------------1 O8 @ j& e1 u1 O! D
Verilog File3 I& _0 E7 h' |3 }
8 w0 _& W, g3 T9 j uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(4 d: J/ u6 x& Y
icwAeYfNum[18:0]), .C(ae_avg) ); |
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