Synopsys R2G flow ! G8 _# ~. `# u$ T# K7 h1 `4 B3 U1. rtl simulation by vcs 3 W7 k0 F; D( T9 ?2. synthesis by design compiler ultra with dc/dct mode- U& [; E6 o% ?+ e0 Y& p' j
3. dft insertion by dft compiler 4 r: A' q% \. N; c4. jtag insertion by bsd compiler : ~" O, u! \& F0 H3 ^: Z/ q5. ICG insertion by power compiler 0 n+ {6 q. C& \# {$ O; f# v6. pre/post-layout STA by prime time - O, e# b# o0 Y! R& K: d. |7. pre/post-layout power analysis by prime time px. d% s+ ?6 k# K% o
8. PnR by IC compiler j& ~' H7 i. ]2 V+ ?8 r+ Z! f9. post-layout SI analysis by prime time si 8 m3 n' x1 Z% J e( ~: e' Q. n2 D! R10. post-layout simulation by vcs
after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing. ! {( @; m0 d$ J- q8 m" S. y; aclean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.
1. magma is another solution ( I. k( X& t' P& `! v1 @( k2. Astro from synopsys# o; o4 l/ D. y& g! A' ]
3. FirstEncounter from Cadence- r( A" a( U1 T
% H& S$ U( a1 [4 _7 C
All with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.