請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
+ Q/ X; N" ^" C& ~1 M. ?  d# q想要用軟體直接 run 到 IC Layout 產生 die photo,
要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
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+ h2 G8 ^& N% |7 gdesign compiler + Astro ?
% a3 W; v0 Z" B* p# I
' {; M$ E- x; C  E" l/ k2.
% T2 a9 o( k6 U" ]( q  R0 y3 o7 Dsynopsys IC compiler ?

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. ^+ s; b7 o" G3 k: icadnece virtuso ?

lee100

Synopsys R2G flow
! G8 _# ~. `# u$ T# K7 h1 `4 B3 U1. rtl simulation by vcs
3 W7 k0 F; D( T9 ?2. synthesis by design compiler ultra with dc/dct mode
3. dft insertion by dft compiler
4 r: A' q% \. N; c4. jtag insertion by bsd compiler
: ~" O, u! \& F0 H3 ^: Z/ q5. ICG insertion by power compiler
0 n+ {6 q. C& \# {$ O; f# v6. pre/post-layout STA by prime time
- O, e# b# o0 Y! R& K: d. |7. pre/post-layout power analysis by prime time px
8. PnR by IC compiler
  j& ~' H7 i. ]2 V+ ?8 r+ Z! f9. post-layout SI analysis by prime time si
8 m3 n' x1 Z% J  e( ~: e' Q. n2 D! R10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
! {( @; m0 d$ J- q8 m" S. y; aclean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
( I. k( X& t' P& `! v1 @( k2. Astro  from synopsys
3. FirstEncounter from Cadence

All with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好