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徵求記憶體6-bit data in 64個字組,不過不要用陣列的方式,很感謝大家提共意見,不過都不是實際記憶體電路的VHDL,我想要的是一個column decoder,一個row decorder,使用port map latch 64個,輸出要使用三態閘,個人想法如下:
p3 F8 D% r! K/ x @LIBRARY ieee; }$ I2 y; L p9 I0 D
USE ieee.std_logic_1164.all;
1 u8 Z. w, G/ O2 pUSE ieee.std_logic_arith.all;
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ENTITY memory_64 IS
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mem_in : IN std_logic_vector ( 5 DOWNTO 0 );9 r3 i2 b9 J" R9 P% W1 `
mem_out : OUT std_logic_vector ( 5 DOWNTO 0 );
/ E/ J# O9 R7 X* I clr_l : IN std_logic;/ P/ c& N$ d1 k
mem_addr : IN std_logic_vector ( 5 DOWNTO 0 )5 U0 E1 m/ w# a3 B7 G" [( v: I
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-- Declarations2 f1 M; W4 }" h- o
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END memory_64 ;. I; z+ ^, F3 v& C3 b2 z
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--
" z8 y# n# m* o9 Q( d9 hARCHITECTURE arch OF memory_64 IS4 o' d* o2 Z5 y1 T2 y' A' [# }, ~% o
-- column decoder
; O/ L- Q h9 S$ I' R3 o! G% o3 p" Tcomponent mem_coldec
2 d. g$ Q8 t; n8 b, h& h PORT(
- b6 V, ~ { G col_addr : IN std_logic_vector ( 2 DOWNTO 0 );
; s4 G, \0 ~) j( y col_sel : OUT std_logic_vector ( 7 DOWNTO 0 )/ ]+ q e$ v, f) ]( U0 q
);
6 O$ U R. e2 z8 Pend component;
7 e, U5 l; }) W7 X" U-- row decoder
2 E/ q3 y, U7 o- E8 ccomponent mem_rowdec
4 U. p, S( E4 u6 R- ^6 Q2 T PORT(
9 z( Z7 G4 C) ?$ P3 n1 I b, o; T row_addr : IN std_logic_vector ( 2 DOWNTO 0 );$ l# ~) \; h. r7 Y/ Z
row_sel : OUT std_logic_vector ( 7 DOWNTO 0 )3 S$ o0 S/ m/ y, W9 I$ O
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end component; . H( j2 E4 A# I2 J* [1 |4 n
-- latch array ! S7 Z7 \0 K) L8 B# E; Q/ q1 P" P* ^
component latch_cell" ~# ?; D* N5 @# @# X, y" u
PORT( 0 n* h3 v: U4 e; X7 Q+ k7 s
clr_l : IN std_logic;
" y& i: t+ M) ?# C# s( t3 {8 H8 w col_sel : IN std_logic;
0 `4 F% a2 a* w row_sel : IN std_logic; - k( F& n8 E6 R. Y% l2 e( L
data_in : IN std_logic_vector ( 5 DOWNTO 0 );
' Z! U- Y8 f4 F! X! H& { data_out : OUT std_logic_vector ( 5 DOWNTO 0 )- Q* F8 X0 ^: W, f! f# l' x$ A
);
$ C* `. a) N9 u* wend component;
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6 u, Y% k( B2 F9 usignal smem_out : std_logic_vector ( 5 downto 0 );! y; r, e) m- `2 K# P( s$ M- `
signal scol_sel,srow_sel : std_logic_vector( 7 downto 0 );
" r' A9 D4 c$ ^4 x5 h5 x1 UBEGIN
0 T% P# M* v6 b! M- E; Z( U u_0 : mem_coldec port map(mem_addr( 5 downto 3 ),scol_sel);6 } J" J q) n% z, r( o3 \
u_1 : mem_rowdec port map(mem_addr( 2 downto 0 ),srow_sel);
3 c: I/ d# n# u# y+ N g0 : for i in 7 downto 0 generate -- column generate
* @% i2 A/ |3 s9 v- K f; v9 S g1 : for j in 7 downto 0 generate -- row generate
+ d' [3 t0 Q$ X% S u_2 : latch_cell
, w( X+ l) _5 g# k8 F" { port map(
8 X' U+ ?" V1 ?; E col_sel => col_sel(j)," _9 y' o6 x/ s+ F
row_sel => srow_sel(i),
, x3 Q6 e; i" \1 g! j: p data_in => mem_in,
+ o, Y6 q& B+ A/ y8 T; R/ ^. ? data_out => mem_out(i)" |- c1 q4 j" d8 ~% D
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end generate; ( [% a1 G; F4 c/ n
end generate;
9 ~' N$ M3 {" J% u8 L/ MEND ARCHITECTURE arch;
) Y" @( q) {1 g6 g不過模擬很久,始終沒辦法寫進我想要寫的位址,試寫了很久,但是始終寫不出來,所以請大家幫個忙,不然那些範例網路上都有,有點急,請大家廣發建議,感謝大家! |
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