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回復 4# 的帖子
1. Using technology file to create a library4 z7 T( M2 {5 j/ S
2. Do stream in with cell type definition file. Specify some special layers' number. IE : Boundary Layer is 63.% J: \; {7 U) Z# t
3. Open new created library, and create some metal blockage if need.
. U+ K) ~1 {, B9 I, W/ B4. Do smash if need.
( n) |, n! C# U# s5 ^' H5. remove some unnecessary extension txst. IE VDD ---> VDD1 x3 }1 w" D! f* V9 S1 c
6. Define power,ground as well as in/out port+ J/ u; k7 G/ W3 Q/ X" R
7.Extract Blockage,Pin and Via by using command auExtractBlockagePinVia.# z! j! c% ^! }7 g# [' q2 S3 F3 T8 O
+ Y% X1 X0 O; FThe processes listed above is my method to do data preparation. Maybe someone know other best way for this issue. Please share it with us.# o0 j/ {* }* Y: i9 v' D: Z
-->我要怎麼做才可以把 ANALOG中 重複性較高的部份交給 APR去做?
7 J5 Q) [3 `6 Z! ]2 J3 \# [; D, CI don't understand your question. Do you want APR toll to place and route your analog block? It is a bad idea if your answer is yes. |
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