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Analog / Mixed Signal Examples
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Behavioral Models of ADCs
! i1 M& Y4 ?- O. j! U\ams\sampling\; sampling_101;
0 }( \$ B) F6 K3 u+ c7 \ Sigma-Delta ADC 1st order modulator $ cd \ams\adc\; dspsdadc2;
9 G) `9 X* B# N2 a; Z t Sigma-Delta ADC 2nd order modulator $ cd \ams\adc\; dspsdadc3; + l# F, _" W" o
Sigma-Delta ADC 2nd order modulator discrete time (switched capacitor prototype) $ cd \ams\adc\; dspsdadc4;
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! q q* a# @% _5 O) ~9 z8 z' E- _: {Behavioral RF
6 q. w1 S8 m5 b9 ~ Measurement of Lowpass Filter Freq Response $ cd feed_fwd_2;
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PLLs
$ w4 ?5 r% K+ m/ }9 |6 t VCO with phase noise $ cd 3 d, |+ u& ]! Z7 e m* `* X* U( n
Pll with freq domain instruments $ cd \ams\pll;
- n5 R& ]6 h/ a) H; U, R+ h8 J# Z8 O# b Pll fractional with analog compensation $ cd \ams\pll; 4 }$ N1 a% n; H
Pll fractional with digital compensation $ cd \ams\pll; + s W/ ]& {" _4 |$ s3 g
Pll optimization (Nonlinear Control Design) $ cd \ams\pll; $ R8 X K; f/ U; V
Carrier and Symbol Timing Recovery (NCO->ADC) $ cd \ams\pll; carrier_timing; % q: O0 `1 X/ z4 p# i! i& B
Carrier and Symbol Timing Recovery (Fractional Delay) $ cd \ams\pll; timing_recovery_1; |
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