Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes
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! T" V. p. X  k5 @+ jKaran Bhatia and Elyse Rosenbaum
Department of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
: j- [( t6 X; o& ?/ b1 n2 o7 Z. V  x8 ~1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
; |7 `' n! V8 t- G
9 B; H3 N( b2 l7 \* fAbstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
  m9 _  t" n  o) z- vinvestigated. The current compression point (ICP) is introduced to define the maximum current handling
) j/ g/ z6 [7 a& h9 r7 w5 Xcapability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
performance of the structures investigated herein.

semico_ljj

The dual-diode circuit has been found to be a suitable
5 C9 ?! \) l+ t6 G. }& t" iESD protection circuit for GHz-frequency CMOS
! f+ `+ V# L# A% u& O- BI/Os [1]. Layout-optimized ESD diodes provide a
: L. @" W' H+ F7 F# Q* i: Yhigh protection level per unit capacitance (C),
minimizing the performance degradation they induce
" A7 N5 p& Z" c" H, k( mon high frequency I/O pins.

mousestack2003

感謝大大分享這些資料∼
5 d) t; }/ }+ ]7 E2 O. v0 e- }: {
讓我們了解led的一些事情∼

majorchen

權限不夠,真想看看layout guide要注意什麼...
真是可惜...

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

dike

真想看看  與工做相關
小弟最近剛好正在研究ESD中  謝謝

allenearl

发现一个很好的网站,有很多EMC&ESD设计方面的资料,完全免费的.
www.gooemc.cn

hing

很棒的參考資料，謝謝分享！

yoyoseven

謝謝你的分享
* {* Q1 |6 x$ ]3 k現在急需esd的防護方式