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Bit rate and protocol independent clock and data recovery+ L/ ]( _7 G2 t+ Y i
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A design for a bit rate and protocol independent clock and data recovery circuit (CDRC) for use
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7 F& |1 _' K3 zin optoelectronic regenerators is presented. A conventional phase-locked loop (PLL) has been 4 A6 V) K; \$ r: C' W
6 N' M# z$ R& |7 S- m+ vextended to a combined phase/frequency-locked loop by adding two additional frequency detectors (FDs). + Y& f+ B3 U, r8 K
5 G& g+ n& P2 p& lThis architecture guarantees reliable clock synchronisation of the input data with different line 0 {) m5 Y- S. g, F4 e% ] @
" F* S' C# F0 Y7 _5 Zcodes over a frequency range spanning multiple octaves
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