hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs
2 J: u, K& Y. C" k) [
2 t3 f' t% r" _7 q6 ?2 d要怎麼定義用
plot LX??
# F9 [) y* T* U, f" k
請各位幫忙一下

小朱仔

直接下.op及.probe
1 E/ d6 ?$ a' X& S7 |, R& j找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.
1 O1 o; ?3 h8 X* f* H* X

For your reference.

0918429587

CAB_BS    LX28
9 k0 D; F+ e) K: F& A# ACAB_BD   LX29
9 l* C) K# ^1 y+ o
其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
這是 CGDBO  CGSBO CBGBO

) N  x% o( M# m! C不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
An example for your reference...

5 K( y6 D4 l5 S5 w----------------------------------------------------------------
/ V1 L. E5 v  u* ?6 A$ \***** Gate Capacitance Plots *****
, J: S7 B5 M, _: s' Z/ U5 v& A.lib 'your_component_model' lib_corner
.temp operational_temp
. f4 X% z6 i. g# o" W1 Z. I" {.option dccap=1 post
2 h' P6 O, l/ z0 c4 e  b0 Lm1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
vg n_gate gnd 5
vb n_bulk gnd 0
.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
4 ~* |* j" i! e. w. [( A+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
" A! |/ h( y* b+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
.ends

* S: U' I8 `1 ~  W+ v----------------------------------------------------------------
Six capacitance are reported in the operating point printout
( J; F1 P% K; X# p3 h( d    cd_total = dQD/dVD
    cg_total = dQG/dVG
& C# n2 T) j" m) q% S    cs_total = dQS/dVS
- q( a6 S6 `/ H    cb_total = dQB/dVB
3 Z( B, h: H) J; o! D* P) @9 i    cgs = -dQG/dVS
    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
1 s' q( i9 B) U! q5 boverlap capacitance, and drain-bulk and source-bulk diode capacitance.
- @3 w, _2 z- B' C7 X
CGG = dQg/dVG
CGD = -dQg/dVD
% ?& E5 k* |$ s! l# NCDG = -dQD/dVG

- q! V. m1 {6 h; N9 P3 C% f- O- gThe MOS element template printouts for gate capacitance are LX18~LX23
  O5 w! P6 g7 D3 F' _# nand LX32~LX34.
5 }# R" c7 q: F7 l" i
1 j* Q4 R$ p; k/ ~. I- QLX18(m) = dQG/dVGB = CGGBO
LX19(m) = dQG/dVDB = CGDBO
( {3 D1 ~* x5 `+ qLX20(m) = dQG/dVSB = CGSBO

LX21(m) = dQB/dVGB = CGGBO
LX22(m) = dQB/dVDB = CGGBO
LX23(m) = dQB/dVSB = CGGBO

LX32(m) = dQD/dVG = CDGBO
LX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO
, K! N+ `6 \% F( a
The equation shown above is for an NMOS with source-bulk grounded
/ k# o) [( I! w. [' \. Yconfiguration. Refer to the user's manual for more detail ^^