[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

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5 b% K; \$ |1 q& c因為無法回覆, 所以開新文回答....
. D$ Z4 Z' v9 b  z$ oABT={2'b00, DATA, 4'b0000};
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/ _7 j# v7 C" a2 u) i5 CVerilog 常用的operator
– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
- S' z, K2 A1 w6 I# }– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
– Logical operators: !, &&, ||
8 F: p9 i- C  ^1 s3 K, n: r– 2’s complement operators: +, -, *, /, %
  f3 S( ]  \! `1 A; L– Relational operators: >, <, >=, <=, ==, !=, ===, !==
# ~; _+ @5 Z0 t) Z7 T4 P$ n# m, {– Logical shift operators: >>, <<
. @$ P: Z( d1 a' y& ?: u9 B% g– Conditional operators: ? :
' b6 Z6 Q' R  h0 j. t– Duplication operators: {n{ <exp> <,<exp>> *}}
– Concatenation operators: {}
給你參考一下