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This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter
+ L/ Y9 h3 X1 i2 R1 Q! E6 i9 s, cAttenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
8 E s6 K* ~+ e, x8 O$ z% k5 Non par with commercially available PLLs, while being relatively simple to design and use as
6 a$ P) y& l" n' ^3 P* l4 {an on-chip solution. The main difference between the JAC and PLLs is that the JAC does7 N: l! V# C+ o6 ^) Y' I+ M
not guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In2 _. f+ b- Y+ f; s
the following sections the effects of jitter, present methods to reduce jitter, and application
6 e8 u. J% D8 {2 [5 R0 Hof the JAC will be discussed.8 I c% ]" w# l4 m$ f9 s* S* U
: E0 J. N# m1 b: c. |, A
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