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Software Support * l" k9 t9 p" t4 R2 X$ E
- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i. 4 W) h4 g8 k N% B6 Q
- N& H( d2 P/ @; h
Platform Support / n: v, u7 ]7 j% l
- Microsoft Windows XP (32 bit)
1 I& m; i, Q$ o: p e7 W$ B5 ?6 }& N, S/ e
Device Support $ P& ^! C0 P7 F
- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported. ( Y# j5 ~/ S8 m: m4 l" }$ L
8 X* p! A' B3 a$ Q$ @) a% tNew Features
7 H: |% A. n) i" W* g' w" ^General New Features and Changes
/ @& Q5 s" ?& F- Supports "Create New Memory Part" for all the designs.
! r% z6 C0 K1 Q" X" i- DDR and DDR2 SDRAM designs for Spartan-3A.
4 p3 [$ P$ e/ G7 p' A/ S& W- DDR SDRAM is supported for Virtex-5.
$ a! H9 Z# J" w0 u' ?. L- l- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM. 0 U! b. K6 b, D9 Q6 i+ G
- MIG now pops up the design notes specific to the generated design.
/ w. i. d# G% a" B2 h0 E$ ^- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs.
( w6 d. ^ Q- }: Z5 G6 Z' T, J* d- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes.
N/ \( F8 I; J: M/ {" J/ O' U0 Y& ^- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2. . B% F3 d( l% G- m
- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A. 5 s9 Y" l6 h0 s% R- _: k4 d
- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST".
8 E# o$ q, Z: ]- Default setting "DCI for Address and Control " is changed to "unChecked".
6 A% c. v4 v; b0 }. k4 `" h1 H- Frequency slider is changed to editable box in the GUI.
% x- C/ H) a# }9 j9 r5 a- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names.
4 G! F. P. `' K4 d" I- Removed console window when running MIG through CORE Generator.
0 f2 z; P3 Q9 g, O2 z- WASSO table (Set Advanced Options) accepts only numeric characters.
" |" U4 y; N9 k: _- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32.
" w5 Y& b5 |7 `5 d( S% P- Provided web links for all XAPPs in the docs folder of the designs.
4 i8 h' s' f# Q- Provided link to Data Sheet instead of Log Sheet in the output window. " T9 o8 T$ A( D5 H( E1 E1 b" Q
- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window. ) h ~0 ^0 G6 X8 b. B
- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank. 8 M8 o4 k0 Z3 N7 \1 o* L* e
- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition.
2 z* K7 o3 F7 }8 e! u$ s: I8 I1 c8 q2 }1 O+ K, y
Virtex-5 New Features and Changes
. Q, ~; u$ c+ c+ v/ ?* m' fDDR2 SDRAM ! I/ C Z: _) B
- New controller with several high-performance features. All the features are described in detail in the Application Notes. 7 Z" h0 C' a9 `1 {- ?8 \
- Enhanced data calibration algorithms for higher reliability. * E+ `& D# G; E! x; y* O
- Bank Management feature is supported.
D* Q; P4 P9 C. u" v4 Z- Supports VHDL. L1 V+ A4 o2 k" {
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear.
: j. ^$ V2 B$ P! C- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus. 7 v; K$ W$ ~: @7 h* w' K, z3 ^
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions.
8 _1 [" p5 h, D' a4 Q* S3 Ta. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
: ], J5 ^( N/ v8 @0 Y; y' {2 M( N0 ub. WASSO is applied to all the memory interface signals. 3 p& e+ G8 h0 }
c. Signals such as "Error" outputs are not part of the WASSO count.
9 y: H# A# W' G1 o1 ?. [. Z4 Q
, i5 o- w' c" j2 i& n4 f; PDDR SDRAM ! [5 D" e% l1 i! e
- This is a new design for MIG. Supports Verilog and VHDL. : t% A1 ]$ Y' z9 ?
- Bank Management feature is supported. 5 \- m$ q7 v. L7 O& D, r3 j
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. & A, x: B: v% ^0 A: i! l( T3 z
2 Z5 s$ U+ y2 @( n
QDRII SRAM
" p. Z' R7 f, `! D- Added support for VHDL.
$ s i$ W$ ~7 _: e( x9 O: l; @( v: Q- Added support for 72-bit designs. / j; _8 b3 ?& Q4 ~# U" [5 i9 K% Y4 u
- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay.
/ x5 ?3 A) q8 ]2 C$ w- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6
$ K8 @6 a) X! _" I- n- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons.
( k& r7 N3 T ~: B- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
) A* `9 O1 `; `6 I; Ha. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
! i& M3 o7 L: v+ L- ~" pb. WASSO is applied to the output signals only.
1 ]( ]1 ?! l0 g8 F
$ ]- A0 i; z& V5 s. bVirtex-4 New Features and Changes
. S$ I( \" r/ {6 `: v' `( m' ZDDR2 SDRAM Direct Clocking
/ J9 m& q1 [5 h/ @8 m. b; q' Q- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design. % g+ `& {1 @! ^9 k+ V" R
- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins. 4 F) V0 v% l8 Q1 {0 l
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
: Q! [# `6 z0 v. E- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options. 9 d# _) q$ t# y- k" y$ E% F8 H2 i# R, x
- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers.
* O0 t. Z8 b: f. A8 b% @) ~- a- Removed all TIGs in UCF. The reset signal is now registered in every module.
! n7 N! m# i2 j/ {6 W- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
; j8 K* P9 y" x" Y" C3 f- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. ' D/ d% o6 J1 u" o7 T
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
8 K0 ?4 \0 e& k- Replaced `defines with localparams for Verilog. / s8 l( W+ @' f0 x
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
7 G2 d7 l& N- \! G* G- Several state machines now use "One-Hot Encoding". ) R" e6 B; F" {7 I$ U
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. 3 }. z& C3 D$ V! b# Y% H
- Signal INIT_DONE is brought to top module. 7 R* \: p; d5 D# T5 [
- Removed the UniSim primitive components declaration from VHDL modules.
: x( Q6 ~( ~0 q& ?# f$ ? }! `3 @6 E- We now support all multiples of 8-bit data widths even for x16 memory devices. . A( o* L* @! O
- We support memory devices of speed grades -3 and -667. / W, z5 q( i$ ~- _7 w! j
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. [- \4 W7 e; g
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 2 A# n( N, Y$ s5 \
b. WASSO is applied to all the memory interface signals. - x% a- w. f% D. K
c. Signals such as "Error" outputs are not part of the WASSO count. , A2 ], x; v3 J1 R! R
: I$ h$ D% \% H# \) O5 _0 FDDR2 SDRAM SERDES Clocking
% E9 z5 J' R7 x- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note.
' i+ t ?- t1 ]6 q: `( r- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. T( L+ h4 l$ k: a% X3 f
- Support for ODT. ) G u5 W+ i# K, W: Q0 u3 x
- DQS# Enable is selectable from GUI through Mode registers.
5 Q3 e5 O9 V' l0 J7 E- A- Removed all TIGs in UCF. The reset signal is now registered in every module.
& |: c$ M6 e8 @( n2 [6 N6 ~) Z4 B- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
; e3 W: X0 f0 E5 C0 _, M- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. 9 L' Q" u4 @( ]8 F6 D1 r0 ^$ Z
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
, H/ n: |: s5 x" L, O5 M- Replaced `defines with localparams for Verilog.
+ t/ a9 J$ ~8 A6 W- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. 9 W; P/ m+ M: E- F, G, T& f
- Removed the UniSim primitive components declaration from VHDL modules. 8 B+ q R# D; [4 @$ K9 o b+ c) X& C
- We now support all multiples of 8-bit data widths even for x16 memory devices. 5 L+ ?. l: M8 L: A
- Signal INIT_COMPLETE is brought to top module. / N% N% E# n" R( i
- Memory devices of speed grades -5E and -40E are now supported.
( j% ]2 n! b& \( E; e- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 5 Z& Z& C( I* w- T3 ]
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
! X' e' y8 h6 l. l$ x; B( eb. WASSO is applied to all the memory interface signals.
* y' O% z4 D6 {4 N6 s2 V: Tc. Signals such as "Error" outputs are not part of the WASSO count.
7 @- m2 K7 N1 X m# S( M; G
: ^+ d, r& l* g( {, `! E: W4 _DDR SDRAM
# {: W# q4 }% H( {+ C- B$ X7 x# j- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 7 a, E4 h( Z/ _6 i
- Removed all TIGs in UCF. The reset signal is now registered in every module.
( V& x- h: n7 Q+ N7 |- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. . E4 `) I6 [& c. v" z8 V; d
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. : [: D: W9 L+ @+ `/ a. K" V
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
; R4 M- {/ ?) E- Replaced `defines with localparams for Verilog.
; l: y% w8 }3 U- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
7 g+ Y5 p/ h3 t$ O# P5 T- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
9 p% j9 _( W+ r5 w* J/ f' l8 y- Removed the UniSim primitive components declaration from VHDL modules.
" }! c( W0 M# d+ L8 ~- We now support all multiples of 8-bit data widths even for x16 memory devices.
0 C, u: _1 H4 A8 k- The signal "init_done" is now a port in the top module. ( `: c% ?3 g, X( p/ k' c8 R% ?
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
. H# p8 P% l( b' w9 T% Ia. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. # R: R3 i# ^6 O$ ^
b. WASSO is applied to all the memory interface signals. + T1 I' r6 C2 D3 o2 s
c. Signals such as "Error" outputs are not part of the WASSO count.
) ^+ `* D% i9 M$ z5 S" r
, Z! p# D+ h$ H) m: SRLDRAM II 6 L+ y( U2 R2 q
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. $ f U) k4 _ x; L( I$ Y
- Removed all TIGs in UCF. The reset signal is now registered in every module. 3 ?6 m4 C3 s4 L( ~
- The design now uses CLK0, instead of CLK50 and div16clk.
1 _0 x9 v3 B. h% |4 W4 P- D- CLK200 is changed to differential clocks in mem_interface_top module (Design top).
% s( ?, e+ ?) @7 r* g( k3 Q- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal.
7 z8 i& a R2 R( ~ Y+ T2 L# _- Removed unused parameters from the parameter file.
% a: s+ D! d1 J1 v( u {7 K( Y- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. " h/ A5 R; Z* h6 s+ e# m7 N1 l
- Replaced `defines with localparams for Verilog. & c+ i7 O. g1 w! B) a4 J
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
+ \7 _6 b' Z1 ]- Removed the UniSim primitive components declaration from VHDL modules. . s, c: R0 P. i& z
- The signal "INIT_DONE" is now a port in the top module.
) \ P$ @3 r, w0 }) \% c2 {1 ~- H- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8.
$ o* i6 R) z, t q6 V' {3 ^- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets.
8 d+ q- o- g6 B4 S6 N. z- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file.
& p+ F6 Z! r; U# l) }- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
$ y5 a4 f8 N0 ~0 H- l, ^6 h; C* Ma. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ( S1 z! \2 e( H% Z6 r0 n+ ?0 q
b. WASSO count is applied on output signals only for SIO memory types. ! R% u% [5 l+ n
c. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool. : ?( N ]+ K! m+ Z) z4 p# c
) b+ i0 o. O' g( q" ]QDRII SRAM
\* s7 _ `! I {3 {- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
5 }7 y' n7 m6 e- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic.
5 S- j5 a' o3 x- Supports generation of designs with out DCM. * k* L3 p5 C6 p
- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC.
0 X g; K8 R* {% D! q: V9 ^, M- Removed all TIGs in UCF. The reset signal is now registered in every module. 3 F7 [( h* M# s9 s, m% A7 c9 J$ p ] h
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 4 U2 M6 z* M2 Q" U, w
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. & B/ F7 g5 {) A$ M
- Replaced `defines with localparams for Verilog.
1 @% g% Q2 z# z' m$ L- |- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. ! n. J! T0 {$ b* Y7 j g1 O
- Removed the UniSim primitive components declaration from VHDL modules. 7 |9 o9 v- z, s) c+ X. y
- The signal "DLY_CAL_DONE" is now a port in the top module.
# C& V* F" W4 U, q- r3 F: f- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. 3 w) U( E4 H) e
- Added support for DDR Byte writes. $ m3 z8 ^9 A/ T; P6 Z
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. . q, c/ L( {2 N! P4 z' j
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
) V* Q) H' q; h* K) Nb. WASSO is applied to the output signals only.
6 H5 g/ |( @; j- ~+ X# x8 `0 r2 kc. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool. . [4 G$ Q( n3 x& n
$ W G% @9 r) n9 [% @DDRII SRAM
) I2 y. ^+ |% ^$ D. e& B* e* S- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. * T! w6 {7 M$ l) ^& l, H: Z- ~+ @+ m5 B
- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic. + V8 W( ^8 s+ x$ [% e% q
- Supports generation of designs with out DCM.
" q, @; E, r" ]' X1 t1 ]/ e& r- Part CY7C1526V18-250BZC has been removed from Memory Parts list. & M0 W+ C$ z8 |% k
- Removed all TIGs in UCF. The reset signal is now registered in every module.
$ Q" ?1 p8 `% D- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 6 G. k7 f4 e6 K% z4 z
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 1 h5 E9 w7 C P% s X
- Replaced `defines with localparams for Verilog.
' a0 t* _2 N# X! h8 U- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
# U+ V) f/ V, K* C" t- Removed the UniSim primitive components declaration from VHDL modules. @; e! f' n: U; S/ c5 |9 D
- The signal "DLY_CAL_DONE" is now a port in the top module.
" H, T6 }+ J/ e9 o9 E/ Z- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
- l2 ~! u, V- }0 }- Added support for DDR Byte writes.
2 {9 \3 D( e6 Y3 ^+ v" R0 _) f+ g/ w- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
. M0 }* h% q, v1 S! y4 w! D oa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. - b# d) ~0 W3 v; I
b. WASSO is applied to all the memory interface signals. 8 L* N0 W2 U K! d, Z) u, F/ t0 x* |
c. Signals such as "Error" outputs are included in WASSO count. |
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發表於 2007-7-24 12:23:39
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