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Cadence SoC Encounter 8.1 Update Seminar
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想了解Encounter最新8.1 版本強大的新功能嗎? 想知道Encounter 8.1如何協助眾多設計成功案例嗎? 我們將展現Encounter如何讓您的晶片設計smaller, cooler & faster,也提供您處理大尺寸晶片設計的解決方案,趕快參加Cadence益華電腦免費的Encounter 8.1 Update 研討會吧。
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時間:
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Nov. 14, 星期五: 09:00am – 13:30pm 5 A& B |! H8 T
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新竹國賓大飯店13F 會議室A&B (新竹市中華路二段188號)6 [- X+ R! ]9 U D5 I: A
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名額有限,請即刻報名!(http://www.cadence.com/tw/events ... ion.aspx?eventid=16)
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09:00~09:30 / Registration
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' D. Q% T/ M1 z% m8 `4 K5 P5 s1 \2 ~09:30~09:40 / Automatic floorplan for design exploration to get the best result5 U2 V# d {) m% f, o, v
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09:40~09:50 / Balanced clock tree to reduce process variation effects $ i, ~# Q7 Z5 s0 @8 w i& G2 A: j
* G% I( r, b1 x4 b0 D! I# l09:50~10:00 / 32nm support for the very advanced technology , D; o+ V* |7 u* d2 c6 F, s2 f$ i
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10:00~10:10 / Post route optimization and SI closure productivity
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10:10~10:20 / 100% MMMC support in the entire implementation flow- m) C& @; N( Z4 g9 S
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10:20~10:30 / Dynamic power optimization and low power CTS for power reduction% J! M; ~$ D- V/ B' m: F2 R& ^, }
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10:30~10:50 / Break
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. o0 Q+ q U, `* l. A4 p# R10:50~11:00 / Encounter Power System for new generation power integrity analysis & U6 J% f6 i+ a' G/ v
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11:00~11:10 / 3 very advanced statistic applications for better performance
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11:10~11:20 / Active Logic Reduction Technology (ART) to handle big chips& \7 C* t, c1 T X) _* Y4 y5 j
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' N' e; e* a2 |" B11:20~11:30 / Constant run time and memory usage improvements! }" J y6 |5 H& Y
* D/ h4 u' z" A' g3 Z11:30~11:40 / End-to-end parallel computing support
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0 r: O( @9 `3 g2 G11:40~11:50 / Encounter Foundation Flow for ease of use and productivity gain; A# t& z: X0 y# L* Q" ^& R: F. j
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12:00~13:30 / Lunch |
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