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Single end--->單端輸入(從P端輸入)
% _! C9 u& u# V% b% m, wDifferential--->差動輸入(LVDS,,等)
% }" w. h3 Q, h( l7 D* x: k如果CLOCK頻率不是很高,可採單端輸入GCLK pin,再從內部去除出所要的CLOCK頻率.4 V5 s! t7 K* G6 j' v$ @/ }7 V
/ N+ [$ [' h- Q( g若要用DCM,從Xilinx Architecture Wizard(在ISE Accessories--->Architecture Wizard)去自動產生所要的CLOCK頻率.Wizard 會產生 .vhd,.xaw,.ucf檔.把.xaw加入design.(利用ISE add source)以下是以單一個DCM instance作例子.5 Q" u8 y$ @3 e* Z M; o: m
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EX: (輸入75MHz--->>輸出50MHz)0 Y6 D+ V( f6 H$ q' ]6 v
entity ClockManageris
- p( q- h ^+ }; M1 o6 a5 [; Z5 LPort ( clk_50mhz : in std_logic;/ J0 I% l1 J) B0 q% x( {1 r6 Y
clk_75mhz : out std_logic;+ ?) F, _/ [! {
clk_75mhz_180 : out std_logic);
' L: q3 X* c* g v8 N7 `- Wend ClockManager;) M% r- [0 x: n) [3 K5 `
architecture Behavioral of ClockManageris% P- C9 u. ~/ k4 m1 L
component clkgen_75mhz3 m) ^2 L8 e7 P3 A3 U& N
port ( CLKIN_IN : in std_logic; z7 e V) ^( j0 ^- i( P k2 c
RST_IN : in std_logic;
7 l4 \3 m1 B2 q' i; TCLKFX_OUT : out std_logic;
& i5 j! S+ {/ Z& [CLKFX180_OUT : out std_logic;+ t* |% w# V* Y' ]8 I1 w
CLKIN_IBUFG_OUT : out std_logic;
' O& Q' D% i7 p& ~' FLOCKED_OUT : out std_logic);- Q6 @3 P: C, }! \+ y" @+ V* h
end component;+ Z j3 T% B, D# g0 l" u/ M
begin0 J' Z H/ [, w
gen_75mhz: clkgen_75mhz% s& v: W3 p" q
port map( CLKIN_IN => clk_50mhz,
$ v* R4 y- S; oRST_IN => '0',
4 A$ G! W2 r! N" E0 l$ q1 \CLKFX_OUT => clk_75mhz,
9 `# k7 f7 L2 Q9 y) N: O4 x/ pCLKFX180_OUT => clk_75mhz_180,
3 y7 F. O2 \( U) x$ G- H; ~% UCLKIN_IBUFG_OUT => open,
! j# w) ^4 v5 U) v7 i: f5 N+ c/ vLOCKED_OUT => open );9 K$ m& Q8 `9 @% ^
end Behavioral; |
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