hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

; Y, t4 R; p  L2 f) f1 R6 H$ ^要怎麼定義用
! R; }* m8 |& \9 Aplot LX??

請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

/ N) _$ T( Z* G" Y' X! s3 e' D/ MCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.
! W4 o( u" f0 ]1 j$ ]" V1 i
, v" m2 J4 ^1 J( Q5 u2 d( j
For your reference.

0918429587

CAB_BS    LX28
CAB_BD   LX29
! V/ t! J% \% F# k: O
+ d, }1 H8 o0 f: F6 n* ~其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
' x9 Q- _; v- `4 w這是 CGDBO  CGSBO CBGBO

不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
An example for your reference...

0 v' c1 K) f. {) T- M----------------------------------------------------------------
3 D- y! A6 |( c; W***** Gate Capacitance Plots *****
: Z! k/ h9 `- T3 k.lib 'your_component_model' lib_corner
.temp operational_temp
' s  T3 l: y) t.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
/ n9 v# y! Q5 f/ E$ p* X2 ^vd n_drain gnd 0
vg n_gate gnd 5
vb n_bulk gnd 0
! k6 ~0 m& E: n& L0 @  B3 X.dc vd 0 5.0 0.1
: S) w. Z2 W1 P.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
9 u  t1 z! [$ N* q! M3 o1 ^+        CGS=par('-lx20(m1)')
, W9 ]8 `7 t( \4 G* T( E9 x4 ^+        CDG=par('-lx32(m1)')
$ e9 A4 I+ A) x4 f( T( B! K" D+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
9 o6 E+ _* g: z) n# x4 x+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
$ J/ F" r) |* W# n.ends

8 q$ S: I9 v5 I1 a----------------------------------------------------------------
Six capacitance are reported in the operating point printout
    cd_total = dQD/dVD
5 F) {( t" U9 E    cg_total = dQG/dVG
    cs_total = dQS/dVS
    cb_total = dQB/dVB
, _3 i# ^$ [) X/ B+ t8 X    cgs = -dQG/dVS
    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
overlap capacitance, and drain-bulk and source-bulk diode capacitance.
3 B2 @( Y  M( n8 U
CGG = dQg/dVG
, u$ f8 l6 w6 f) h/ TCGD = -dQg/dVD
CDG = -dQD/dVG

The MOS element template printouts for gate capacitance are LX18~LX23
and LX32~LX34.

LX18(m) = dQG/dVGB = CGGBO
& x0 W( o2 g' ELX19(m) = dQG/dVDB = CGDBO
, N8 t: S) O0 q( g0 o1 R5 MLX20(m) = dQG/dVSB = CGSBO

; L8 t6 w9 l" r4 vLX21(m) = dQB/dVGB = CGGBO
LX22(m) = dQB/dVDB = CGGBO
LX23(m) = dQB/dVSB = CGGBO
, q; D  j0 D' t9 K2 L2 b) \1 h0 j
LX32(m) = dQD/dVG = CDGBO
LX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO
7 b1 P0 M0 c& X7 n) C6 l* A
The equation shown above is for an NMOS with source-bulk grounded
1 I) {0 x9 K" a0 A7 R& lconfiguration. Refer to the user's manual for more detail ^^