LVS問題 望大大指點

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使用LEdit90的LVS時，顯示This file is Binary.LVS can not perform iteration.無法進行對比，這是怎麼回事呀

m851055

是比對檔案中路徑的問題，若有需要詳細說明把netlist PO上來................

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原理圖
" e+ h0 }' S4 c. N9 B* SPICE netlist written by S-Edit Win32 7.03
5 i0 X- k6 u' A( b3 G7 H0 ~3 E* Written on May 27, 2009 at 16:57:24
! ], J/ F# \& p5 U- E5 E+ _' ~7 D0 V) x* Waveform probing commands
3 l3 {; A: A/ e4 t.probe
% h# ~  D/ T4 p9 H' {& s  H.options probefilename="G:\tanner\Nand2_1.dat"
+ probesdbfile="G:\與非門2.sdb"
8 I6 i) y) q8 t/ ^1 C+ probetopmodule="Nand2"
( X* V; J: F0 y6 o5 t" L; s+ o* Main circuit: Nand2
. i4 n' }1 \2 ?( uM1 OUT A N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
4 R, l- l' @& AM2 Gnd B N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
7 C1 b7 u. u* a1 Q0 lM3 OUT A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
; V# h& d+ `* PM4 OUT B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
0 r" S! Z8 D$ y4 Y* End of main circuit: Nand2

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版圖
* Circuit Extracted by Tanner Research's L-Edit Version 9.00 / Extract Version 9.00 ;
* TDB File:  G:\tanner\Nand2.tdb
4 K- K, i4 Z8 G" G, T* Cell:  Nand2        Version 1.07
* Extract Definition File:  G:\lights.ext
* Extract Date and Time:  05/25/2009 - 15:05
' s7 [6 Z" g, I; r' [* Warning:  Layers with Unassigned AREA Capacitance.
*   <N Well Resistor ID>
$ _+ P+ B' l# n) c9 [- e6 {4 G*   <Poly Resistor ID>
*   <Poly2 Resistor ID>
*   <N Diff Resistor ID>
: O. H1 s0 s) A*   <P Diff Resistor ID>
*   <P Base Resistor ID>
  e; F  g: }3 T! J/ g* Warning:  Layers with Unassigned FRINGE Capacitance.
*   <N Well Resistor ID>
*   <Poly Resistor ID>
) ^5 s2 T. Q0 I% J*   <Poly2 Resistor ID>
# ~" S0 K) h' ~) z, f" V9 ]*   <N Diff Resistor ID>
4 [8 }; V/ F7 g3 X$ o*   <P Diff Resistor ID>
*   <P Base Resistor ID>
4 R  J; I3 S! L/ ?. a; V# I) ~* d*   <Pad Comment>
*   <Poly1-Poly2 Capacitor ID>
2 S- ?& [0 D5 |! M0 t. Y* Warning:  Layers with Zero Resistance.
! [& u6 ^! t  ^2 \$ b- O: i# J) [" B*   <NMOS Capacitor ID>
/ e5 f! s& f4 Q( i1 O*   <PMOS Capacitor ID>
! ^: l5 m/ }# n. O  S+ |' F*   <Pad Comment>
& _$ c5 z9 }, E6 d7 v! m5 m*   <Poly1-Poly2 Capacitor ID>
5 m. @7 T- G- O( \# h1 \
* NODE NAME ALIASES
*       1 = B (12,-14)
1 e2 [: ~) a5 k1 E" \*       2 = A (-16,-18)
" Q& Z5 v* Q! ^9 N- c/ J) R*       3 = OUT (-2,-21)
8 a6 J5 c% C. a8 W*       4 = GND (-30,-35)
- G, L% A7 p" T4 V( t& _! `*       5 = Vdd (-32,14)
5 r; P$ ^) ?6 V$ u- P9 u, i& SM1 Vdd B OUT Vdd PMOS L=2u W=6u
* M1 DRAIN GATE SOURCE BULK (3 -3 5 3)
+ y1 \) w8 F9 }* o& C- W% k8 YM2 OUT A Vdd Vdd PMOS L=2u W=6u
8 J- M+ v5 v8 l6 ~+ m1 T3 v. B$ z* M2 DRAIN GATE SOURCE BULK (-5 -3 -3 3)
% m# P; t# H* z3 ~M3 OUT B 6 GND NMOS L=2u W=6u
* M3 DRAIN GATE SOURCE BULK (3 -31 5 -25)
$ V. q* k1 b$ n1 U: xM4 6 A GND GND NMOS L=2u W=6u
* M4 DRAIN GATE SOURCE BULK (-5 -31 -3 -25)
, b3 {. e: q0 m* Total Nodes: 6
* Total Elements: 4
- M9 G* |5 q- b. W  B* X* Total Number of Shorted Elements not written to the SPICE file: 0
* Extract Elapsed Time: 0 seconds
+ K5 c! f7 U1 l* [, P% b.END

m851055

與非門2 files name改為英文名稱.......................

xjyy

我宅了一周 沒想到栽在路徑上  萬分感謝 ！！！！！！！！！！