請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
想要用軟體直接 run 到 IC Layout 產生 die photo,
" p5 M% B! I' z0 @$ ^要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
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design compiler + Astro ?
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2.
% n3 u0 C5 z+ b) H$ T' Ksynopsys IC compiler ?
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( r9 v. l9 W8 e8 Hcadnece virtuso ?

lee100

Synopsys R2G flow
1. rtl simulation by vcs
. Q! }1 j2 e/ G' Z; m' b2 [. B2. synthesis by design compiler ultra with dc/dct mode
3. dft insertion by dft compiler
4. jtag insertion by bsd compiler
5. ICG insertion by power compiler
6. pre/post-layout STA by prime time
7. pre/post-layout power analysis by prime time px
8. PnR by IC compiler
+ ^3 \( r. _8 l4 @2 o8 X( U; ~5 f9. post-layout SI analysis by prime time si
10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
- G  \4 Q) f- a; Z1 pclean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
2. Astro  from synopsys
3. FirstEncounter from Cadence
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" U# U2 p8 @. KAll with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好