請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
想要用軟體直接 run 到 IC Layout 產生 die photo,
. m4 T' K- h# a5 @! a3 B" f0 \要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
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design compiler + Astro ?

2.
synopsys IC compiler ?
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& [# f3 D% F5 ^; K8 x  G$ V# m3.
cadnece virtuso ?

lee100

Synopsys R2G flow
- E6 v: }/ b9 a$ H* e; e1. rtl simulation by vcs
2. synthesis by design compiler ultra with dc/dct mode
3. dft insertion by dft compiler
4. jtag insertion by bsd compiler
5. ICG insertion by power compiler
7 I" C3 J+ {5 i6 M' l6. pre/post-layout STA by prime time
$ P1 b5 x3 S; I7. pre/post-layout power analysis by prime time px
8. PnR by IC compiler
; K1 C7 e6 ?7 Z" }+ B! \9. post-layout SI analysis by prime time si
$ Q$ e( y- s+ n/ }10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
$ J) {" J7 {5 V+ p: T8 Gclean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
2. Astro  from synopsys
3. FirstEncounter from Cadence
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7 i* x( E4 s- EAll with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好