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8 Failure Modes, Reliability Issues, and Case Studies 228% @, N% S# {3 C4 b, c( b
8.1 Introduction 228
6 w; N9 A, Z1 e5 f T8.2 Failure Mode Analysis 229
! [! o9 K1 ?1 d( N8.3 Reliability and Performance Considerations 238
& l; p. R1 s' D; [3 Y( C5 }* F3 \8.4 Advanced CMOS Input Protection 239, y( ]- t' R4 _$ T U6 p
8.5 Optimizing the Input Protection Scheme 242
- `% U% G, A! K9 t# `8 J8.6 Designs for Special Applications 249
k2 X. e0 {6 P, u, m6 u8.7 Process Effects on Input Protection Design 253
# @5 N* m2 v, \6 m9 w. P8.8 Total IC Chip Protection 255
' s, z" M% L/ B2 E8.9 Power Bus Protection 256
x) d r3 ]' \6 _( i# V9 n8 v' m8.10 Internal Chip ESD Damage 258 I- G) m* J- E% {7 o8 j! b4 ~4 v
8.11 Stress Dependent ESD Behavior 263
^% e ?& t: t4 I8.12 Failure Mode Case Studies 267; ]1 u3 l! K+ y0 P& h! k! J
8.13 Summary 271
0 ]' n1 p. K- u) d/ G1 T* sBibliography 272" }7 U& I7 _, a. }7 e$ C' O
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