Overview on ESD protection design for mixed-voltage I/O interfaces

semico_ljj

Overview on ESD protection design for mixed-voltage I/O interfaces
3 x* x6 `+ t2 a# ?& f% u, _with high-voltage-tolerant power-rail ESD clamp circuits
in low-voltage thin-oxide CMOS technology

: P/ I. g1 i  a0 t1 \7 [Introductory Invited Paper
1 ]" ?6 u0 h" w& v; yMing-Dou Ker

. r1 N) m. C7 _* z- D+ m( D7 g

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ulysseslaii

goodgoodgoodgoodgoodgoodgoodgood

heyunpro

goodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgood

cedric761193

The ESD is easy implement but difficult to design.