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For ESD test (HBM)& T) |+ n. \4 q- d' R% |: V
The following are the test combination:6 p! v7 o" h E) [6 P
1. Power to Power
! h. g% e) ]( `% n3 h2. Power to Ground
0 ^& U& ^5 |; `% H3 ]3. IO to Power. R5 h8 U/ W6 H! {
4. Io to Ground
+ R2 X }0 u" W, d+ p, x5. IO to IO/ T+ z; s& G. b4 M' m# N
(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)- b1 s. {9 r, ~! C* f) Y4 x2 V4 G8 K
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the total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)
7 U( V% P1 V) c' CFor example: You have IO1/IO2/IO3/P1/P2/G1
$ \, S' |# f! l N, @5 N2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)5 q, B4 r, b# Z- u/ L V
So for high pin count it will take a lot of time. But it won't take more than a week(for one chip).
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For your reference. |
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