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8 Failure Modes, Reliability Issues, and Case Studies 228
% E& p- h# c, g- c2 X8.1 Introduction 228
9 x5 x4 [2 S! u( w, X5 ]4 J8.2 Failure Mode Analysis 229 F$ D; D6 r" S; A' m7 y5 x: M
8.3 Reliability and Performance Considerations 2382 _2 N3 z: S2 x
8.4 Advanced CMOS Input Protection 239
& N: E% l8 x1 p1 ]# I" ?1 B8.5 Optimizing the Input Protection Scheme 242
6 Z3 F# D: n' |$ w( g, e& m8.6 Designs for Special Applications 249& H; x: W# A! j
8.7 Process Effects on Input Protection Design 2538 j& S* l& t% _9 n. g
8.8 Total IC Chip Protection 255% V" B( C& t. I o, g* D' A
8.9 Power Bus Protection 256; ~% K9 D9 y6 f
8.10 Internal Chip ESD Damage 258
3 n, z, {. Y+ @; z8.11 Stress Dependent ESD Behavior 263
1 w6 j9 n) I( J1 M8.12 Failure Mode Case Studies 267& U q" P! @2 e5 x( Q6 i
8.13 Summary 2711 ]# `; B7 m7 `! o7 Y9 O
Bibliography 272
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