Item
1 R; @9 F5 f+ n2 I! U | SH77722 (SH-NaviJ2) Specifications
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Type name+ b3 ]; Q' g9 x6 w1 m! {+ Y
| R8A77722DA01BGV8 [. P- [% |5 l2 P2 }
| R8A77722DA02BGV
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Power supply voltage3 d: p( {( s% G/ l( W1 y
| 1.15 to 1.3 V (internal),
s/ ?" z. `) @( l3.3 V and 1.8 V (external)
6 \/ f1 N- J) o- j+ d" L' v9 L | 1.2 to 1.35 V (internal), : B; g+ z/ X2 \/ d. w3 X
3.3 V and 1.8 V (external)- f" O# ?# {0 o4 v$ N2 @
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Maximum operating frequency
8 e. X4 ?4 ` s" D | 336 MHz/ i! H7 N- K# K3 B) l
| 400 MHz2 `1 |6 O: K: E) ^) S- p* q$ `1 I
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Processing performance+ a% q6 g6 T# ^9 B$ S& T$ U/ ^, `
| 600MIPS, 2.3GFLOPS
8 X& M5 V7 v8 m, n3 V | 720MIPS, 2.8GFLOPS
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CPU core
9 c* O' i1 x. @, y @8 p | SH-4A core
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On-chip RAM
$ K! F- {: t( W | ILRAM: 16 Kbytes
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Cache memory
+ x" x+ [, J9 f: b1 _ | 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data5 y! Z- v* ]$ X+ l5 B/ N( y
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External memory
" L* `, ] @, t: g$ H( M7 F | DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus+ L# m& C3 @* v2 q* ?% h
| DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus
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SRAM or ROM directly connected to extension bus
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Extension bus) W' [; l6 c, E
| Address space: 64 Mbytes × 3
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Main on-chip peripheral functions
& H5 [3 l9 W9 C | Renesas Graphics processor(2D/3D)
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Display control: outputs for two screens (digital RGB and LVDS) N C2 h) E9 p8 v
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Video input interface0 A. D6 D% w" A0 L& F/ O
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SD card host interface × 2 channels% b* }" ]+ l; W
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USB 2.0 host/function interface, T0 h( C: _0 O( w
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FM multiplex decoder4 Z2 [5 e( L; Y) c( j
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Controller area network (RCAN) interface × 2 channels
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MOST interface module
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Various audio interfaces × 4 channels- a6 q, u! u" s! r9 A4 I
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Dedicated DMAC × 26 channels
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I2C bus interface × 2 channels o# ?0 O* [" w2 b$ W2 v4 f& D
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Serial communication interface (SCIF) × 8 channels
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Remote control interface × 1 channel6 p3 ]# B$ J) @3 c6 g
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A/D converter (10-bit) × 4 channels8 S, V$ `4 f2 H5 g: v5 w1 e
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Timer × 9 channels
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On-chip debugging function' Y4 N8 y0 Q. J+ g& ~8 S* Q" x6 G
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Interrupt controller (INTC)
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Clock pulse generator (CPG): built-in PLL frequency multiplier
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Power-down modes
% }4 P% E; U* ]5 X | Sleep mode
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Module standby mode f( e% I ~. P: j
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DDR-SDRAM power supply backup mode" _2 K% t' Y, i6 b X/ j
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Package' @# _7 E5 C5 a' s/ E* e; j
| 449-pin BGA (21 mm × 21 mm): F6 J$ l) s Z. u! k8 ^* Y
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