hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs
; j/ r# M8 I% M3 ^; z% y
要怎麼定義用
2 ?7 }( r; U" B' Eplot LX??

1 h. E) N) U( d$ s; d% r請各位幫忙一下

小朱仔

直接下.op及.probe
1 k6 L5 j# h- c0 ~找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

' l. x$ Z6 f; W( t; D4 c; ]6 X/ j8 qCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.

6 k) l6 a& J" D# ]' d4 |
* }7 n, s1 G! T& Y/ vFor your reference.

0918429587

CAB_BS    LX28
; u" m* F& W' d; p- c$ vCAB_BD   LX29
$ r+ _; T- e  x+ g
其他我找不到
* r/ e- ]* E5 q3 g+ ICgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
3 r/ @7 b% O& n: t這是 CGDBO  CGSBO CBGBO
/ s# }7 O6 ~4 N7 v. {  [5 _
  s# d2 o- K. ]- g9 H1 X不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
An example for your reference...

----------------------------------------------------------------
4 I: _- z$ y& o; _- ~3 u' a***** Gate Capacitance Plots *****
% s! t( ?$ N6 N1 W3 a3 x.lib 'your_component_model' lib_corner
.temp operational_temp
( v; ?) W9 m# F7 p.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
- }+ \9 ^5 A- W$ B$ [vd n_drain gnd 0
vg n_gate gnd 5
# o) I# h) o- ]% J7 a5 E* L- Q- gvb n_bulk gnd 0
6 V2 @1 }+ V& W5 D9 q8 u* r5 K.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
! n" x5 e* `7 @) q0 Z/ |' [+        CGD=par('-lx19(m1)')
# k0 J( S& ~& r" a+ x+        CGS=par('-lx20(m1)')
, n& R7 k, S5 H5 T% k+        CDG=par('-lx32(m1)')
% \- G6 D7 J9 [6 r: u; ?+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
5 w4 k6 ]7 I% B4 f0 e2 g  p.ends
; T& O% q8 {& S  l  L, t
----------------------------------------------------------------
+ u& B+ {* Y$ f& [% WSix capacitance are reported in the operating point printout
: g6 _  i- N. L. T- T    cd_total = dQD/dVD
% ^6 W) P3 f1 i0 _: k    cg_total = dQG/dVG
    cs_total = dQS/dVS
' o' q  o& Z5 D: d+ g    cb_total = dQB/dVB
    cgs = -dQG/dVS
* e& i, f3 V% w/ e/ r    cgd = -dQG/dVD
8 _/ n( m6 c: ~  [. Q( GThere capcitances include gate-drain, gate-source, and gate-bulk
9 \, K8 k% l( N0 v5 x  V& Toverlap capacitance, and drain-bulk and source-bulk diode capacitance.
9 Y6 d. x' J1 A! ^% Y+ h, S
# U4 a+ I4 q/ w6 g( D3 j. _/ CCGG = dQg/dVG
0 b: S( N( Y7 BCGD = -dQg/dVD
+ q8 h' |0 X6 T) aCDG = -dQD/dVG
+ ~7 E/ c# e- R3 Y
/ q3 N% w. `: p+ _1 zThe MOS element template printouts for gate capacitance are LX18~LX23
and LX32~LX34.

LX18(m) = dQG/dVGB = CGGBO
6 \( D* t4 N) _% w" s9 m" YLX19(m) = dQG/dVDB = CGDBO
LX20(m) = dQG/dVSB = CGSBO
# a/ {6 R( j3 o' A+ j; e
LX21(m) = dQB/dVGB = CGGBO
2 [" X; R- K, ?) g' RLX22(m) = dQB/dVDB = CGGBO
8 s3 U' T3 H+ i$ ?LX23(m) = dQB/dVSB = CGGBO
' t, [4 \) }) C2 |- o% a$ f: B
LX32(m) = dQD/dVG = CDGBO
LX33(m) = dQD/dVD = CDDBO
* J3 ]& y7 c. R6 i# U, qLX34(m) = dQD/dVS = CDSBO
3 d2 m! x. Q4 G; |* j+ I. s8 R; ]
The equation shown above is for an NMOS with source-bulk grounded
configuration. Refer to the user's manual for more detail ^^