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回復 4# 的帖子
1. Using technology file to create a library
6 ^8 d Y5 i0 G2 q- I- w2. Do stream in with cell type definition file. Specify some special layers' number. IE : Boundary Layer is 63.
6 h+ ]5 A/ j$ G5 w3. Open new created library, and create some metal blockage if need.5 Q* Y. ^0 K5 j% o7 Y7 F, |
4. Do smash if need.! r+ _1 @, b3 H4 m
5. remove some unnecessary extension txst. IE VDD ---> VDD# a# \+ X" S/ q1 |0 ^2 G: M- S
6. Define power,ground as well as in/out port
' e# W u4 r D& \) d4 G4 Z" ?0 f* C7.Extract Blockage,Pin and Via by using command auExtractBlockagePinVia.
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4 a8 N) ]6 |0 ^ a& O0 j3 p! pThe processes listed above is my method to do data preparation. Maybe someone know other best way for this issue. Please share it with us.6 S9 W: O% x0 l, A& p2 I+ ]
-->我要怎麼做才可以把 ANALOG中 重複性較高的部份交給 APR去做?$ G" p4 |6 E" y( _' k1 b! e% I
I don't understand your question. Do you want APR toll to place and route your analog block? It is a bad idea if your answer is yes. |
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