在鎖相迴路中如何決定迴路頻寬K呢？

option318

　如題，請問先進們，在鎖相迴路中要如何決定迴路頻寬K呢？它又和Phase margin、Gain margin有關嗎？ :f17

kmchen3089

回復 #1 option318 的帖子
(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一
否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
pll ,且亦有unstability issue
9 ^* O8 l: n9 y" B1 a5 Y* U. T(see Charge-pump phase lock loops paper by Gardner
& `( ~7 E' N* K: |IEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
- e% d. Z3 X6 @% k" N+ _) x(2) loop BW is related to jitter (or phase noise) ,and locking time
  i& L! U/ g. z8 G* L# C% Cso you have to consider loop BW  from jitter & locking time  spec
2 p6 u0 G6 d$ w9 G" M(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq
(4) In my opinion ,gain margin is not considered in pll design

jasonxilion

gain margin is not considered in pll design？
i don't think so.
+ O6 {: w, d7 }' O7 u) K2 uisn't it dealt with the stability?

賴永諭

書上都有講哩...加油看看先....
9 w4 Z+ C" L( h. p/ ~8 Y應該不難找到哩...