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Senior Physical Design Engineer
: n3 C1 p, J8 I% S2 Y公 司:A famous IC company: p! \7 ^) @% _+ p$ u
工作地点:南京
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Key Responsibilities 9 n k* s! D2 @+ ^) m
Depending on experience, key responsibilities will involve some of the following: " n9 T; {$ ?# i; c
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
0 A- o+ T9 O2 d0 Q& w- |As a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
5 X6 k5 m9 _' [3 SLeading a team of physical design engineers and resolving the technical related issues. " r ?0 b" A6 ?* d
Crosstalk analysis, power analysis, and static timing analysis.
" T1 [) U9 Z0 \ p& Y5 nWrite scripts in Tcl to improve productivity. ) }1 z, Z" X/ O0 G
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Experience: 5+ years in physical implementation engineering $ S2 o _- t( i& V
4 {; w( j% @( l" `Essential skills
7 `/ B$ S3 [+ [6 dMS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills 5 t! y( ?2 M" O1 H2 x
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.
- x' G- a" \& ]+ ^5 nGood programming skill. Capable of writing Tcl or Perl.
' t0 g7 } U X; h8 jFamiliar with synthesis, static timing analysis.
, n; Y- Y- \. V0 ASelf-motivated team worker, good verbal and written communication skills in English.
! e5 o. U9 m: Z( DTechnical and team leadership proffered. Previous management experience highly desired. P" G q4 a9 h( Z1 a7 K
Experience with synthesis, DFT, and verification is preferred. |
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