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Layout Guidelines for Optimized ESD Protection Diodes5 V9 e/ ~, F! C+ _0 a2 [( |# T
# M5 D5 I3 }6 [5 X! H$ u2 \) wKaran Bhatia and Elyse Rosenbaum
6 }2 N! P5 V2 y+ Y9 MDepartment of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
& O5 k4 c: Q0 g* ?1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
7 d$ e: y, `& W/ @+ Q0 \. l
) d" y$ } w4 }+ IAbstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
/ h X ~# L2 B# a8 T& V( U3 pinvestigated. The current compression point (ICP) is introduced to define the maximum current handling
4 y! {3 R2 r: J! l0 Y8 tcapability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
}0 L$ j" u5 T1 @performance of the structures investigated herein. |
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