|
AMD Geode LX 800@0.9W處理器
General Features
2 s" u: z1 B7 [" C* \3 C) z■ Functional blocks include:
" o7 I8 j+ S7 t% s— CPU Core
. D: z7 {# {: `6 ~; [— GeodeLink™ Control Processor# ?( @# W1 o1 O. b% s/ H \! p
— GeodeLink Interface Units$ b1 ]& J, |4 k0 W. q
— GeodeLink Memory Controller4 i8 B" v& V% J0 v. @
— Graphics Processor" B% n- L* s2 |6 l, ]
— Display Controller! z' X2 [8 M+ J5 U
— Video Processor' y" b( `7 ? f# k" L% c# P
– TFT Controller/Video Output Port
8 l. u. ~) R2 m/ i' B/ ]— Video Input Port8 J z" p; O( T1 ~8 V
— GeodeLink PCI Bridge* \1 T1 c+ t, O' F# E9 M3 \
— Security Block! O, P+ n, f. u0 \! A$ w
■ 0.13 micron process: W/ r# d3 M) E
■ Packaging:
6 A7 |$ G. p' w! ]- ?7 m! q9 w# Q— 481-Terminal BGU (Ball Grid Array Cavity Up) with h& C# o, q' [) {* F
internal heatspreader- V d3 n8 H( ?' W) v/ F
■ Single packaging option supports all features0 T6 Y6 o; p' H( [
CPU Processor Features
! h f2 m H; p8 a6 V V■ x86/x87-compatible CPU core
4 H# [/ `2 S! j■ Performance:
, {* E+ G& G# h9 \— Processor frequency: up to 500 MHz) I0 W O8 b8 t2 W5 u" H7 ~
— Dhrystone 2.1 MIPs: 150 to 450! b% \- {7 v" I3 s3 x6 @
— Fully pipelined FPU- O j5 u3 t) p
■ Split I/D cache/TLB (Translation Look-aside Buffer):& b2 J: X7 v; _" s& u& S F
— 64 KB I-cache/64 KB D-cache
" u# ~/ N6 a& @8 C— 128 KB L2 cache configurable as I-cache, D-cache,
W- v2 w6 c: w2 Eor both9 L3 f: |0 ^. J
■ Efficient prefetch and branch prediction: d4 L8 i) E* w9 q3 V
■ Integrated FPU that supports the MMX® and7 h; w1 b! F8 U/ y H- u4 _
AMD 3DNow!™ instruction sets$ D E9 h' [/ S4 B; J# q$ w
■ Fully pipelined single precision FPU hardware with
2 e& C6 a' t2 Y4 y# o: ~1 jmicrocode support for higher precisions
1 c( k4 i9 C7 U4 Q# FGeodeLink™ Control Processor, a( {5 ~* {" q# j- X& i; i' [
■ JTAG interface:; a3 x- W, }4 t7 [" N, y, U
— ATPG, Full Scan, BIST on all arrays
9 C6 T7 Z4 c8 H5 e$ D— 1149.1 Boundary Scan compliant
( k) [% _, c: R: s' f/ g6 X2 K■ ICE (in-circuit emulator) interface
: U' J" H1 u" l$ ~■ Reset and clock control
3 K( Y; ^1 o0 X$ u U■ Designed for improved software debug methods and
9 C8 G$ @) {, c% A+ K5 F2 }; Xperformance analysis
. N+ m0 }) h( j$ y# ~2 H■ Power Management:; s( W& y7 t: ?" ]9 a: x# E! [' j
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @1 ~( o. ^( W* k q. m, Z' H
500 MHz max power6 K4 [. ~7 W2 H! ~5 m! V3 c$ K3 ]7 t
— GeodeLink active hardware power management! k) [: Z& r: l4 A$ ]5 @
— Hardware support for standard ACPI software power
. x9 }, P( s/ P w. Omanagement
0 t' T s- _7 O; w— I/O companion SUSP/SUSPA power controls
3 l% w2 P A# ]$ m— Lower power I/O0 D7 C; E% M/ F2 Y1 ?
— Wakeup on SMI/INTR# }+ T4 Q8 M6 S( a s
■ Designed to work in conjunction with the2 l; b d0 V7 p7 P: ?9 c
AMD Geode™ CS5536 companion device3 Y' B- r9 s% I# N; u' e
GeodeLink™ Architecture$ A- u/ m2 ~. ~) D) U7 h
■ High bandwidth packetized uni-directional bus for
6 w- a' r( i: g, Y Linternal peripherals
2 Y/ K5 Y* B7 X5 }; k( L) M■ Standardized protocol to allow variants of products to be5 ^' |8 A: n1 q; b \, @8 T. ?
developed by adding or removing modules
7 q* W: W0 z8 w9 ~■ GeodeLink Control Processor (GLCP) for diagnostics& P' _. q7 X% ~ R; W4 ^/ u
and scan control
/ I o& T0 z: z3 ^# z* r7 H■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
4 G4 w9 Y$ F5 I& MGeodeLink™ Memory Controller
4 k) b' [9 ]! W: s% m■ Integrated memory controller for low latency to CPU and
+ Z0 E" I8 E" B1 C9 h( c2 Z; Oon-chip peripherals
+ n* i: d4 D8 T$ h2 l# g9 n5 T■ 64-bit wide DDR SDRAM bus operating frequency:
+ Y3 ~" }' D3 R& S2 U, f+ p— 200 MHz, 400 MT/S" J6 }1 _2 o5 k4 {1 D
■ Supports unbuffered DDR DIMMS using up to 1 GB9 r, R4 }, k8 M' i& s
DRAM technology0 |% _7 c& t4 l0 T' ]2 Q3 ^
■ Supports up to 2 DIMMS (16 devices max)
2 L7 y% ]3 X! ^: K. \: z+ w b2D Graphics Processor
' ], f1 B2 h1 n5 G■ High performance 2D graphics controller6 h" ~) D+ `6 V) o
■ Alpha BLT
% V6 m! u2 W' ?4 @" ?2 S/ e8 D9 Q& Z■ Microsoft® Windows® GDI GUI acceleration:: B+ [, W: ? t. I1 E
— Hardware support for all Microsoft RDP codes4 z" ^# z0 ?' R0 i4 U8 q
■ Command buffer interface for asynchronous BLTs
1 p' s/ w6 h& n# R0 b& K■ Second pattern channel support/ E" v0 F+ `1 ]/ |# O
■ Hardware screen rotation |
|