Calibration techniques in nyquist AD converters

cnasic

Table of contents
List of abbreviations
+ i* S2 u+ u  A- V, r7 @! [+ }List of symbols
; ~6 x/ v' M8 hPreface
8 G! L) `( X# A2 h1 Introduction 1
1.1 A/Dconversion systems . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Motivation and objectives . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Layout of the book . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Accuracy, speed and power relation 7
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
& R/ d: p% I& d, u% Q/ ?3 F5 W) M2.2 IC-technology accuracy limitations . . . . . . . . . . . . . . . . . 8
' B  t! Z* s, m6 P. _2 r0 A7 p2.2.1 Process mismatch . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2
( k1 z' }3 A5 |2 p$ r# H2.2.3 Matching versus noise requirements . . . . . . . . . . . . 11
9 x. H5 j9 u( X$ ?2 s) i4 s9 z0 N2.3 Speed and power . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9 |% c! D5 Q0 _  P" h7 Q7 z2.4 Maximumspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9 Z* Y! {' z! U$ [# M' z2.5 . . . . . . . . . . . . . . . . . . . . . 15
2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 A/D converter architecture comparison 21
3 t( n4 g# d, `3 c- d3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
$ f7 L% C# Q- P5 O% `# S- p3.2.1 Fullflash . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . 26
& o" r# B* A0 @* [% ^2 r6 Q3.2.3 Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . 29
. `: u8 w* x2 x3.3 Folding and interpolation . . . . . . . . . . . . . . . . . . . . . . 33
3.4 Two-step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Thermal noise . . . . . . . . . . . . . . . . . . . . . . . 10
3 Z4 s- X/ N$ _- d) J8 Y: |7 G1 JCMOS technology trends
" Z* r3 V) M" H4 `xi
xiii
: V. k- {% X) f7 Xxvii
( Y6 w6 Y! ?0 E$ S1 e6 m+ NTable of contents
3.5 Pipe-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.6 Successive approximation . . . . . . . . . . . . . . . . . . . . . . 54
3.7 Theoretical power consumption comparison . . . . . . . . . . . . 56
4 e- Z5 [; I  x& j3.7.1 Figure-of-Merit (FoM) . . . . . . . . . . . . . . . . . . . 57
3.7.2 Architecture comparison as a function of the resolution . . 57
. C0 o  J3 [3 I1 P, l' u3.7.3 Architecture comparison as a function of the sampling speed 65
. _. ?5 e0 s$ K6 J4 u. ~2 g7 |3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4 Enhancement techniques for two-step A/D converters 67
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
( d! n8 P# m# ~4 V9 o& K& r4.2 Error sources ina two-step architecture . . . . . . . . . . . . . . 67
' m' Y- x# X9 V+ w0 m/ I5 c4.3 Residue gain in two-stepA/Dconverters . . . . . . . . . . . . . . 69
4.3.1 Single-residue signal processing . . . . . . . . . . . . . . 69
( u2 @6 S( d& A5 X4.3.2 Dual-residue signal processing . . . . . . . . . . . . . . . 71
4.3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4 Offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 75
) m" T5 u  A# b* @* `& j: ]4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 75
- [/ _2 [% J) ]4.4.2 Calibration overview . . . . . . . . . . . . . . . . . . . . 75
4.4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Mixed-signal chopping and calibration . . . . . . . . . . . . . . . 83
4.5.1 Residue amplifier offset chopping . . . . . . . . . . . . . 83
4.5.2 Offset extraction fromdigital output . . . . . . . . . . . . 84
4.5.3 Pseudo random chopping . . . . . . . . . . . . . . . . . . 88
) D9 j+ G" R  h! j9 O4.5.4 Offset extraction and analog compensation . . . . . . . . 91
9 h2 N* }6 [( [4.5.5 Offset extraction in a dual-residue two-step converter . . . 93
: G* D- }' {' K5 v4.5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 102
5 A 10-bit two-step ADC with analog online calibration 103
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.2
5.2.1 Coarse quantizer accuracy . . . . . . . . . . . . . . . . . 106
5.2.2 D/A converter and subtractor accuracy . . . . . . . . . . . 107
! E! b, ^* Q) t! r7 A5.2.3 Coarse andfineA/Dconverter references . . . . . . . . . 108
5.2.4 Amplifier gain and offset accuracy . . . . . . . . . . . . . 109
: W; z) ?6 H3 l  K6 ]5 M5.3 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.3.1 Track-and-hold circuit . . . . . . . . . . . . . . . . . . . 111
5.3.2 CoarseA/D,D/Aconverter and subtractor . . . . . . . . . 111
5.3.3 Coarse ladder requirements . . . . . . . . . . . . . . . . . 112
. k1 c- }1 _+ f4 b0 a0 d5.3.4 Offset compensated residue amplifier . . . . . . . . . . . 113
5.3.5 FineA/Dconverter . . . . . . . . . . . . . . . . . . . . . 114
5.3.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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5 V. s  N' w3 G  MTwo-Steparchitecture . . . . . . . . . . . . . . . . . . . . . . . 105
Table of contents
5.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . 117
8 s4 i9 \! ]  R% G  h5.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
; H8 e* j& c: d3 W( O) N5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
& {( Z& m9 g5 j1 O, S! U' _6 A 12-bit two-step ADC with mixed-signal chopping and calibration 123
7 A low-power 16-bit three-step ADC for imaging applications 149

xp212125o

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tuza2000

good material !!!