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Bit rate and protocol independent clock and data recovery& G" Q* }0 [) M `5 h
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Abstract2 B" v, k* \4 P# E, T
# t$ n5 O( @) n+ i0 r" oA design for a bit rate and protocol independent clock and data recovery circuit (CDRC) for use
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8 V7 v M0 i# ~( Din optoelectronic regenerators is presented. A conventional phase-locked loop (PLL) has been / U" r/ ~4 B( s) |3 X
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extended to a combined phase/frequency-locked loop by adding two additional frequency detectors (FDs). 3 P& |8 ^8 P5 |% z0 R% m/ A- F: m5 |$ j
- x. U: E+ I/ J' O- T( H% ?- _This architecture guarantees reliable clock synchronisation of the input data with different line
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codes over a frequency range spanning multiple octaves
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