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This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter1 t' I5 W3 o7 h. q% N U2 {
Attenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
* D! F$ ?8 j1 ^& J5 don par with commercially available PLLs, while being relatively simple to design and use as
7 I5 T. k* e* r- {# q A+ s8 Ian on-chip solution. The main difference between the JAC and PLLs is that the JAC does
6 L: \4 g! D+ j$ Knot guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In# ?8 ?5 U f2 T/ f- \1 b
the following sections the effects of jitter, present methods to reduce jitter, and application
3 W. j1 N [2 l, m8 Tof the JAC will be discussed.
3 X7 l1 I3 f m6 `9 l/ S: `+ X% d& D# x$ u
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