|
實驗平台~
) j0 t0 \1 K/ u# O$ t$ n/ H& j I「Terasic」Altera DE0 多媒體開發平台,Cyclone III 3C16 FPGA
2 C5 X, \) B, r8 L在建構的過程中(僅放入cpu跟memory ip)9 |7 v7 ?8 p9 j* H6 g
no reset vector has been specified for this CPU
' k4 y/ s: X* R" ano exception vector has been specified for this CPU
7 U" L( x4 D/ Y6 e M! T6 n這兩個訊息,沒辦法完全消除,這兩個一定要消除嗎
* F$ U6 q4 U* q* Y" F* B3 h試過2 S$ |7 y8 W: s( D% |9 }6 O
on chip memory! ^! }. a0 h, r7 R0 N% t, I
sdram
6 R8 Q2 j' w) H9 A2 _# b3 J" S! f用上面兩個去試過所有可能的組合(mem/mem,sd/sd,sd/mem,mem/sd)
4 y8 A5 O6 d& N- [7 {+ Rno reset vector has been specified for this CPU
, F3 M( y& `* I7 h" @no exception vector has been specified for this CPU! r: [3 |1 V6 ~' \# r$ O4 `8 K
總是會有一個沒辦法去除(先選的訊息會被消除)1 G3 ]( A: i2 W% q: I" @% i m0 T
' `9 \5 j$ `# e2 E: a; k
有人有在玩10.1版嗎?請多多幫忙~~, {# ?- i. r& i. s
$ n8 g5 B, n9 n
目前打算~改用10.0sp1跟9.1sp2試試看
% p# V* ^* |8 x9 X' M9 t( m: k. i D' U4 l7 S7 S1 M$ v# J
THX~ |
|