Stanford_Mark Horowitz_Digital MOS Integrated Circuits

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Lecture 1 - Intro and Modeling   
Lecture 2 - RC Modeling and Calibration        
0 j: ]& G! F. R; A4 h( }5 [& I3 h; p  }Lecture 3 Memory Design   
Lecture 4 - Delay Optimization and Logical Effort   
Lecture 5 - Decoder Optimization   
Lecture 6 LE in the Real World   
- d! @' L) d: OLecture 7 Lower LE Gates   
Lecture 8 - Low Field MOS Transistor Model   
Lecture 9 - High Field MOS Transistor Model  
Lect 10 - Using MOS Models   
Lect 11 - Cap Models   
Lect 12 SRAM Column Circuits   
Lect 13 What Makes Gates Digital
Lect 14 Diff Pairs - Current Steering Logic
Lect 15 - Static Sense Amplifiers   
4 d& b5 L0 U7 |7 E* KLect 16 MOS Matching Clk SenseAmps   
0 |/ W/ H3 f9 [7 {/ ^& O9 ZLect 17 SRAM Noise Margins / Noise   
; X6 q+ D+ }) D) z$ D' w% E$ j& P7 VLect 18 - Timing Gen and Array Partitioning   
Lect 19 Adv Clocked Logic   
' Z* `. h6 D7 M8 F7 w: J4 \) pLect 20 Low Swing SRAM   
Lect 21 - Introduction to Solid State   
Lect 22 Threshold Voltage, Leakage and Tunneling

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