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AMD Geode LX 800@0.9W處理器
General Features
; d! n, G& `2 n( ^■ Functional blocks include:$ V1 x4 J, C# b9 V
— CPU Core
$ d% V* ~3 Q" t( W& @& X— GeodeLink™ Control Processor
9 l B- y; B/ y/ {! ]% @% v— GeodeLink Interface Units7 j! H- E- V( {; ~2 u8 j0 S9 B. N
— GeodeLink Memory Controller9 \. O/ [5 X" ^( p) A$ @
— Graphics Processor9 v# O9 M) m6 y/ @8 v
— Display Controller5 q9 J M; ?) h" P+ d
— Video Processor
1 K: ]/ \/ x- C: y @9 e, @– TFT Controller/Video Output Port0 E# n: M, V( u0 ~, R* Z: K
— Video Input Port
7 ]& r/ V7 F$ k& W- ]/ t— GeodeLink PCI Bridge- x* p' N/ `' w: U. t# o
— Security Block
, N% c5 c+ u+ P4 m0 d3 ~9 d■ 0.13 micron process7 q+ R1 f! c5 ^! ^6 d3 Q1 g
■ Packaging:
5 G& D* P2 m+ w. p& c6 k3 w— 481-Terminal BGU (Ball Grid Array Cavity Up) with- v: p% V e) V
internal heatspreader
" C5 u; O! H7 Z" D■ Single packaging option supports all features* _" N( a$ J2 O9 o* O3 D0 P
CPU Processor Features$ `. b+ A2 G Q
■ x86/x87-compatible CPU core
$ ?% K# K1 e0 g" j5 L0 Q2 r■ Performance:
' ]! N- w1 r$ \& }, P+ u" D— Processor frequency: up to 500 MHz$ a3 t9 s6 r( E+ u; q
— Dhrystone 2.1 MIPs: 150 to 450
o7 U3 t" S) o— Fully pipelined FPU/ ~1 ~5 y* p( z; t, T
■ Split I/D cache/TLB (Translation Look-aside Buffer):$ n+ H' m( X* V6 j( l
— 64 KB I-cache/64 KB D-cache( P, J- x$ s$ C2 R. J. c; c3 s
— 128 KB L2 cache configurable as I-cache, D-cache,0 D0 q7 M( a; K0 _
or both9 ^ X! C5 j6 W& K$ a# I5 i
■ Efficient prefetch and branch prediction+ z$ [) U) [. {* H
■ Integrated FPU that supports the MMX® and0 r7 W* ^2 z, j% e" f5 W
AMD 3DNow!™ instruction sets: O. G6 Q4 ?& I7 m: _: o1 ^
■ Fully pipelined single precision FPU hardware with0 O, Z R" {, [8 v% _/ b
microcode support for higher precisions
; m9 N4 b) G# z& \/ j4 o( Y1 qGeodeLink™ Control Processor# \& H9 ^$ r0 ]; J
■ JTAG interface:% A7 L5 j. ]% K
— ATPG, Full Scan, BIST on all arrays
6 Z# H/ x, o( c( o& O— 1149.1 Boundary Scan compliant
( B5 P) X* J( f) z# Q- P■ ICE (in-circuit emulator) interface$ Q! u7 F* s/ f5 y7 B% J
■ Reset and clock control
5 G8 e) |7 @/ L" G9 j■ Designed for improved software debug methods and4 T: ?0 r; z' R8 f0 ?9 }
performance analysis
! A1 o8 Z. ?; G1 G■ Power Management:4 H" c5 m6 I. U! V6 h6 \$ F
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
6 e/ b" b9 Q# [+ b2 i& r! U500 MHz max power
* p. T& I! y/ |2 I4 |, b" u: r— GeodeLink active hardware power management5 T% J/ F+ t' E8 S- ~
— Hardware support for standard ACPI software power% n- i1 |$ M5 [2 ^; V
management3 {" t$ N5 |+ i5 v' K- w, R7 p
— I/O companion SUSP/SUSPA power controls, |9 [0 y6 j4 `" J ]( K4 X2 h
— Lower power I/O
, U! u2 [/ t r* r) }& ^— Wakeup on SMI/INTR
; k6 G3 k# p& v# B' @. ?1 m! {■ Designed to work in conjunction with the: s9 }6 _0 C+ a; D; T
AMD Geode™ CS5536 companion device/ p. G: C6 L! b; Y
GeodeLink™ Architecture
- A- H$ w8 Q4 z3 T _■ High bandwidth packetized uni-directional bus for" Q% B; P: a+ N4 c( W3 g5 a K" k8 m
internal peripherals* D- n) i/ G( i, X; ^
■ Standardized protocol to allow variants of products to be
/ i1 a7 J: \( p& Cdeveloped by adding or removing modules
9 @/ U4 x+ n* ~0 k) I■ GeodeLink Control Processor (GLCP) for diagnostics4 g7 j! N* W; Z% U: |- D
and scan control
0 |# `. [, b4 r$ l■ Dual GeodeLink Interface Units (GLIUs) for device interconnect1 T3 k6 j$ f% X$ {9 S; k* ~
GeodeLink™ Memory Controller: K0 p- y* o- m+ n p, u
■ Integrated memory controller for low latency to CPU and9 b: ^& b9 n- ~1 H; S
on-chip peripherals9 ~0 ]; d5 D+ p8 M# [ X
■ 64-bit wide DDR SDRAM bus operating frequency:' N. b4 \8 g0 i6 K4 p/ W
— 200 MHz, 400 MT/S
/ ]3 F7 o6 {) h/ f% g( s& q2 m■ Supports unbuffered DDR DIMMS using up to 1 GB
4 A5 e0 p9 b, g, ?DRAM technology/ t$ [( V1 I l1 a$ g5 s3 _& e( D
■ Supports up to 2 DIMMS (16 devices max)
! H% R t8 F7 m7 v3 c6 A; ^4 n2D Graphics Processor
1 t' Y# r3 p9 C" N! X■ High performance 2D graphics controller4 h9 x7 d8 r' B* T
■ Alpha BLT' m2 i7 g3 m0 o/ p% U
■ Microsoft® Windows® GDI GUI acceleration:
/ R$ b; f5 m% ~5 g# T' T— Hardware support for all Microsoft RDP codes
1 |, V$ p; X# Z2 ?) B■ Command buffer interface for asynchronous BLTs
9 q$ p, r6 u& e2 j, {■ Second pattern channel support
( x+ k7 `6 M& a4 [5 m$ ~9 Y■ Hardware screen rotation |
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