Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

cnasic

Contents
List of Tables
9 ?% a3 h( F9 d" ^List of Figures
Symbols and Abbreviations
; N! ?6 X, X) G2 U4 cPhysical
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 ADCs in Nanometer CMOS Technologies 3
, b8 s2 n! j, t0 }) k% n) m( H2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Scaling-Down of CMOS Technologies . . . . . . . . . . . . . . . . . 3
) Y' O  Q2 C7 Q2.2.1 Driving Force of the CMOS Scaling-Down . . . . . . . . . . 4
+ n2 R. o) n* X5 C# g( _* E. p2.2.2 Moving into Nanometer CMOS Technologies . . . . . . . . . 5
2.3 Impact of Moving into Nanometer CMOS to Analog Circuits . . . . . 6
2.3.1 Decreased Supply Voltage . . . . . . . . . . . . . . . . . . . 6
9 F0 Z2 E1 n8 J3 ^' c5 y0 y! _. e2.3.2 Impact on Transistor Intrinsic Gain . . . . . . . . . . . . . . 7
2.3.3 Impact on Device Matching . . . . . . . . . . . . . . . . . . 9
! K, P7 |- [& l" J! i% K2.3.4 Impact on Device Noise . . . . . . . . . . . . . . . . . . . . 10
& G0 I2 j& Y8 h: @2 F4 a2.4 ADCs in Nanometer CMOS . . . . . . . . . . . . . . . . . . . . . . 11
! t" v! s; N! T7 B. k2.4.1 Decreased Signal Swing . . . . . . . . . . . . . . . . . . . . 13
2.4.2 Degraded Transistor Characteristics . . . . . . . . . . . . . . 13
2.4.3 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
% O6 I3 `& _6 ~/ F; b& N/ T: H% Tvii
* ?* N7 }1 j7 _$ N3 b2.4.4 Switch Driving . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.5 Improved Device Matching . . . . . . . . . . . . . . . . . . . 17
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+ e) K4 t! V  _+ t! y" y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
# v5 M: \8 O0 @: U; ]" E  ?CONTENTS
2.4.6 Digital Circuits Advantages . . . . . . . . . . . . . . . . . . 17
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
) x" y" e1 r0 j* b' x  i3 Principle of - ADC 19
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Basic Analog to Digital Conversion . . . . . . . . . . . . . . . . . . 19
9 l( _* z$ D' d! [/ W9 x3.3 Oversampling and Noise Shaping . . . . . . . . . . . . . . . . . . . 24
9 U2 ?1 Y3 E" X8 I. }8 D& J- _3.3.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.3 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.4 Performance Metrics for the - ADC . . . . . . . . . . . . 31
3.4 Traditional - ADC Topology . . . . . . . . . . . . . . . . . . . . 33
2 t( {' w, G7 s7 V+ x2 I% e3.4.1 Single-Loop Single-Bit - Modulators . . . . . . . . . . . 33
3.4.2 Single-Loop Multibit - Modulators . . . . . . . . . . . . 37
. L" @' E/ T* a& D$ _/ \, ]$ P3.4.3 Cascaded - Modulators . . . . . . . . . . . . . . . . . . 39
3.4.4 Performance Comparison of Traditional - Topologies . . 46
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
& I9 W# X" Q$ z7 O' c" u/ U4 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: Circuit
Level Approach 47
1 j9 d3 W( A* P8 o4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Low-Voltage Low-Power OTA Design . . . . . . . . . . . . . . . . . 48
; ?  Z' F2 i/ q( _4.2.1 Gain Enhanced Current Mirror OTA Design . . . . . . . . . . 49
4.2.2 A Test Gain-Enhanced Current Mirror OTA . . . . . . . . . . 53
$ D9 W3 g- @3 l" }" ]0 Q4.2.3 Implementation and Measurement Results . . . . . . . . . . . 54
$ T0 q" W- B! Z  q* l2 S4.2.4 Two-Stage OTA Design . . . . . . . . . . . . . . . . . . . . 55
! u% p7 U2 [0 O$ r5 l" c6 w4.3 Low-Voltage Low-Power - ADC Design . . . . . . . . . . . . . . 66
: C! V, M. Z- s& o+ l9 D4.3.1 Impact of Circuit Nonidealities to - ADC Performance . . 66
' n: ]# ^; d7 Q; a8 ]4.3.2 Modulator Topology Selection . . . . . . . . . . . . . . . . . 67
8 o+ \; [. f6 _7 Q5 \4.3.3 OTA Topology Selection . . . . . . . . . . . . . . . . . . . . 69
4.3.4 Transistor Biasing . . . . . . . . . . . . . . . . . . . . . . . 75
7 H7 O' w) D, Q4 g3 N4.3.5 Scaling of Integrators . . . . . . . . . . . . . . . . . . . . . . 75
# z& p' ~7 L4 d4.4 A 1-V 140-μW- Modulator in 90-nm CMOS . . . . . . . . . . . 76
4.4.1 Building Block Circuits Design . . . . . . . . . . . . . . . . 76
7 y2 O; D+ S4 G' K0 Xviii
5 D% C8 d5 n, K' Q6 S' Y6 h4.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 80
0 Z' Z5 l' P* y+ Q. m$ W4.4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Measurements on PSRR and Low-Frequency Noise Floor . . . . . . . 87
& y9 t) F+ r3 F. c4 m4.5.1 Introduction of PSRR . . . . . . . . . . . . . . . . . . . . . . 87
7 F# q% @2 M+ Z* L4.5.2 PSRR Measurement Setup . . . . . . . . . . . . . . . . . . . 88
# {6 p2 s( O2 i  j/ `4.5.3 PSRR Measurement Results . . . . . . . . . . . . . . . . . . 88
, e; E% `% R7 f1 I2 j' p1 O0 q- _4.5.4 Measurement on Low-Frequency Noise Floor . . . . . . . . . 95
4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: System
3 P' }& f$ [4 [- H/ H6 J3 a) aCONTENTS ix
CONTENTS
7 h/ ]* d. O5 I0 X0 J2 N6 Conclusions 149
Bibliography 151
Index 157

scan7510

看不太懂
+ N7 p2 C7 A1 I可能還沒學過吧
% w% f$ E- j1 V0 C: n; p現在只能單純推一下
0 d' E9 p" z/ o4 D; H; J: q0 G謝大大分享

deltachen

謝謝大大的分享~知識因分享而壯大！

jjam

感覺是非常實用的內容
7 G3 f4 _* n2 P, \& O感謝大大的分享~~
1 X" v! ?( T9 A: ^2 r希望能對SDM有所認識與了解