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AMD Geode LX 800@0.9W處理器
General Features: {; ^3 K- x. ], Q6 b
■ Functional blocks include:
: v8 z2 a) ^3 E/ I— CPU Core, {' S# `/ h$ Z9 f j' M
— GeodeLink™ Control Processor
$ o$ |9 M4 W0 U— GeodeLink Interface Units
2 r3 |5 A4 A# G0 ]— GeodeLink Memory Controller5 q6 K1 W: F4 T% b: w( B( M6 `+ n) I
— Graphics Processor/ S% _' ^- b( J2 m; D8 A
— Display Controller
4 d/ {3 l' z* h+ K; u* D— Video Processor. i& a8 q/ F: k
– TFT Controller/Video Output Port
5 B2 y3 w! C. I c& f— Video Input Port6 d3 \6 _! p8 t1 ?5 S* v0 ]
— GeodeLink PCI Bridge; p, G& j0 ?9 Z/ i H
— Security Block% \8 X; k8 K+ [. N2 o6 u5 Y& V. Q9 M
■ 0.13 micron process# f, B7 E1 Z, V) t3 {
■ Packaging:
2 X0 E) P( j) Y2 V/ v— 481-Terminal BGU (Ball Grid Array Cavity Up) with
$ C- C& D" h3 y5 ^1 q( ~1 L" Dinternal heatspreader
+ h% u* r% J3 p7 `■ Single packaging option supports all features
+ W3 K6 n( j% }# ~+ G) a/ ZCPU Processor Features
+ f/ P5 n" u' }# I8 r! P■ x86/x87-compatible CPU core& m: h6 c/ L) ]' H
■ Performance:4 ^# [3 q8 Y! T; I8 E
— Processor frequency: up to 500 MHz0 M7 E6 J4 e$ v2 Z7 i
— Dhrystone 2.1 MIPs: 150 to 450
8 c5 O2 `& U t+ v. V— Fully pipelined FPU
8 P! E. n& ^1 G5 \& C0 f■ Split I/D cache/TLB (Translation Look-aside Buffer):
D H$ Y( v% ^3 C- A— 64 KB I-cache/64 KB D-cache/ a! X3 r6 ?# j c
— 128 KB L2 cache configurable as I-cache, D-cache,3 E( G2 a) K- {0 i& A8 q
or both
2 J2 C3 R9 p* [4 Q4 _! s■ Efficient prefetch and branch prediction3 l. \# A5 c" a3 M% B
■ Integrated FPU that supports the MMX® and
% X; W& I2 }" t7 C% jAMD 3DNow!™ instruction sets
! y8 l! ^3 y, p/ s. Q3 n3 r■ Fully pipelined single precision FPU hardware with8 m) v: Y% c/ t6 b( V: y
microcode support for higher precisions
/ A1 y7 B' I, YGeodeLink™ Control Processor6 ^* z6 m+ j- m8 n
■ JTAG interface:
1 U8 n' c# T' c K— ATPG, Full Scan, BIST on all arrays
! K( c1 R' Y- O0 n& H1 R/ g3 |— 1149.1 Boundary Scan compliant+ l2 _/ m7 O9 F( }' H- k
■ ICE (in-circuit emulator) interface
) J9 j; S9 j- X- F1 C: G■ Reset and clock control/ \$ t7 K- R- @3 {. `( S
■ Designed for improved software debug methods and% d) T: P# N6 \2 F6 K$ `1 {
performance analysis/ t6 c7 Q5 G5 z8 P7 @2 |
■ Power Management:
3 s! E9 K# N: s, Y5 n+ B- m- F6 M— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
/ T6 G7 t4 L; T' B" u0 Y+ T500 MHz max power; ?, m+ ]7 ~$ R; r) Z
— GeodeLink active hardware power management
) T# N- h$ b7 l7 k N+ i— Hardware support for standard ACPI software power8 g+ d8 k' A8 Q: d7 L' H' [
management
, p D9 a) X1 z! Q% F1 E" U0 a0 v— I/O companion SUSP/SUSPA power controls7 N% H7 M/ E9 w K7 w3 Q
— Lower power I/O; M2 X3 l/ {* e j
— Wakeup on SMI/INTR
5 t* v' H+ Y6 {7 d■ Designed to work in conjunction with the8 L% B. e; f/ u. \$ z
AMD Geode™ CS5536 companion device
7 ]0 b$ W( ^1 F- E+ y+ LGeodeLink™ Architecture, n4 D" S, ?5 R6 u
■ High bandwidth packetized uni-directional bus for
+ U% s) P' P2 a5 q# `# Iinternal peripherals
! X: }1 ^, G9 b$ |8 E$ s! f■ Standardized protocol to allow variants of products to be5 d$ W3 r8 O& c# }7 r
developed by adding or removing modules
# g9 o' t3 N1 t& D■ GeodeLink Control Processor (GLCP) for diagnostics0 Q; l7 J0 s9 B+ u
and scan control5 ^3 S) k+ T7 V- M5 F8 {7 s
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
! D V) d2 [: W) n/ q) q' eGeodeLink™ Memory Controller6 l) r1 e. Z+ q/ K/ [
■ Integrated memory controller for low latency to CPU and
8 U- H2 L! l0 | d& o0 ron-chip peripherals
9 ^7 ^/ k) @2 Z( @5 X% ]■ 64-bit wide DDR SDRAM bus operating frequency:
: i& m i' k# H7 O— 200 MHz, 400 MT/S
/ O+ r/ L& Q- g0 u■ Supports unbuffered DDR DIMMS using up to 1 GB* ]# z: K P8 i
DRAM technology5 x, T+ y1 f. L$ i: {0 N8 c* R' y7 x
■ Supports up to 2 DIMMS (16 devices max)% H0 G) V" d) G- o3 I
2D Graphics Processor
0 E. t! ^# t; G; J% j■ High performance 2D graphics controller9 ?) r+ |. w- h7 ]. U% n
■ Alpha BLT
' E2 W8 I9 l) k5 V. W! Q s; H■ Microsoft® Windows® GDI GUI acceleration:
9 f# S8 S( e) z l5 x3 k— Hardware support for all Microsoft RDP codes" l7 S- \" m# p E1 m
■ Command buffer interface for asynchronous BLTs
' ^; M- c6 E3 k8 S■ Second pattern channel support3 r, G; r% q& K8 G3 z8 g k" U; ~# H
■ Hardware screen rotation |
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