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AMD Geode LX 800@0.9W處理器
General Features- \7 N0 L! i' X( K1 M
■ Functional blocks include:
( t( d8 a+ P G$ D— CPU Core# _0 d: L8 H$ P% z; _1 J# |. I
— GeodeLink™ Control Processor4 S; e5 b; S4 y6 c( }0 H
— GeodeLink Interface Units
: b0 R# ]" J- N$ k! j: I& D; a% g, A— GeodeLink Memory Controller- o$ L% c3 t, m( q0 ~" g
— Graphics Processor
6 y8 r6 x' A9 F0 T— Display Controller
8 f9 J; j: w0 _0 ~1 k7 V— Video Processor' ?6 R( M1 I- n0 v
– TFT Controller/Video Output Port1 C& W. e8 b6 g# F
— Video Input Port
\ f; U' o" L8 J. w— GeodeLink PCI Bridge N8 z2 ^! \* v, a, Y% ^9 N" b
— Security Block
2 h9 A8 k2 ]- J+ a; L, m$ \/ h■ 0.13 micron process
- O( G: ^6 W c( O0 a2 _' o7 p■ Packaging:4 q* C! D/ \& P2 Z
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
& m( @# k; U6 U$ ], l7 `internal heatspreader% s/ m% U- z4 q
■ Single packaging option supports all features& {1 ~0 D; o# F: G4 h/ J
CPU Processor Features$ r3 }5 O: `: S7 H% @
■ x86/x87-compatible CPU core) R+ S/ W" _- k/ O; e
■ Performance:
; N5 c7 L# @* l2 g3 G$ O2 h6 M— Processor frequency: up to 500 MHz
6 `% G# ^4 p' h T; a— Dhrystone 2.1 MIPs: 150 to 450
' x7 y2 ]; W- [9 g/ M+ ^— Fully pipelined FPU, E- a; b; Z: s, F- P
■ Split I/D cache/TLB (Translation Look-aside Buffer):- R3 Z }' v' i6 C
— 64 KB I-cache/64 KB D-cache
: h; {* q; H* b4 |$ L6 Y/ B+ ?— 128 KB L2 cache configurable as I-cache, D-cache,
& ]+ Y- p& P1 Kor both& @9 R0 N/ A2 Y" o, z4 [( y/ m. }* N
■ Efficient prefetch and branch prediction
! R+ a- ^1 R1 e" k$ R; Y■ Integrated FPU that supports the MMX® and
- u" l' m3 K- ]AMD 3DNow!™ instruction sets
8 Y3 }6 L2 ?- u3 H8 J, d7 B7 `1 q■ Fully pipelined single precision FPU hardware with, e; a! ^4 M& U, a8 G1 z9 U
microcode support for higher precisions. P$ [& P% B( \
GeodeLink™ Control Processor
: s1 W! x; G7 e n$ Z■ JTAG interface:
\( p1 g+ ?1 Z7 U1 [— ATPG, Full Scan, BIST on all arrays' ~+ a$ S$ z* i, h; j
— 1149.1 Boundary Scan compliant0 a. i% O2 F6 F0 J2 n% R
■ ICE (in-circuit emulator) interface
- K# i) {7 j4 `5 \$ ^' G. f. u■ Reset and clock control
% U$ P! x! Z2 I# |, W/ q■ Designed for improved software debug methods and
' V7 c1 Y* k# n3 P4 D% f8 tperformance analysis
5 k" l' d6 p$ T* v0 O& A5 p■ Power Management:* r& F( d" S* Q4 L4 \2 f
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
# }% |9 K6 q6 G' Y. | a500 MHz max power
3 d2 ^ ?: x7 q/ Z7 _5 R$ x( W— GeodeLink active hardware power management
q( Q$ u n% U7 M: v, v& v— Hardware support for standard ACPI software power
5 e. a+ l$ ^9 R3 b6 P+ xmanagement# n3 W& o; l/ `" O( z$ B$ k
— I/O companion SUSP/SUSPA power controls
( I0 R: x6 h( J+ W3 T* y3 _— Lower power I/O
& O! |8 r- s4 C+ U6 s0 b. w) M# K1 z— Wakeup on SMI/INTR* H( o9 P3 S+ h
■ Designed to work in conjunction with the
9 O6 \' v8 ~- V8 H3 OAMD Geode™ CS5536 companion device" c. x1 t9 ]0 o& ]' c9 w8 X' y
GeodeLink™ Architecture
. |( s# ?7 w& X# F" S {7 a■ High bandwidth packetized uni-directional bus for
& ~3 X9 I" f6 ~3 ~4 Q& o( Zinternal peripherals; e$ x3 [/ X9 C& e3 S7 Z. t
■ Standardized protocol to allow variants of products to be
/ H4 E" Z, U$ C, @ Sdeveloped by adding or removing modules
% b2 v4 ~7 j5 o* o( F$ n4 L4 z■ GeodeLink Control Processor (GLCP) for diagnostics" F) r, S7 z$ r! S, }# ]# A
and scan control
( t# k" D6 Q4 R3 J■ Dual GeodeLink Interface Units (GLIUs) for device interconnect2 t/ m9 U2 E5 h4 `" Y
GeodeLink™ Memory Controller6 e4 l' x1 ], v. n+ K- f' s% |
■ Integrated memory controller for low latency to CPU and" n+ X' [; z* f3 u
on-chip peripherals
- d J& [5 x6 R: c0 I* Z■ 64-bit wide DDR SDRAM bus operating frequency:
7 b+ m9 s' S! J4 L! u% ?— 200 MHz, 400 MT/S
9 I5 n' U/ A6 n■ Supports unbuffered DDR DIMMS using up to 1 GB6 `3 h6 y/ u M% H! c% r- q
DRAM technology
, F% m3 m5 {8 u/ f■ Supports up to 2 DIMMS (16 devices max)
% z& }: ]/ K3 H1 Q2D Graphics Processor/ w% N% Q3 f/ y8 k7 V# `
■ High performance 2D graphics controller
; \/ J- o8 I8 i! K: z" s4 R■ Alpha BLT, f7 Q; Y* ]0 E6 j( s9 v! G
■ Microsoft® Windows® GDI GUI acceleration:
I$ ` }/ `; e$ w1 u; E( V5 a. O) T— Hardware support for all Microsoft RDP codes
* U- p0 @& ~+ h8 w■ Command buffer interface for asynchronous BLTs4 b3 J. y9 {% V. u7 N8 A
■ Second pattern channel support
& c' C1 W( X0 v3 f" E■ Hardware screen rotation |
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