|
AMD Geode LX 800@0.9W處理器
General Features/ S7 V( ^" ~$ E7 i* i8 p& u+ H
■ Functional blocks include:' k: q9 E6 `8 W2 {0 E- M9 J# r
— CPU Core
. S2 U1 _) z- K5 `- k8 a6 P6 s% B— GeodeLink™ Control Processor5 M8 A Q- y1 {4 |3 j! P$ s7 x$ n9 {
— GeodeLink Interface Units
+ @$ d. h' W# b* G% G— GeodeLink Memory Controller6 ]& `9 K1 d% M# ^+ S9 }
— Graphics Processor
: ]+ G' o$ q+ l/ S- r) W. R5 b— Display Controller
a+ B# c, X% p6 X8 A: u* }. |— Video Processor
* M( z& `2 A1 r- K5 a' d– TFT Controller/Video Output Port
/ V' q5 W8 J. J— Video Input Port4 ^+ B( s# c! V
— GeodeLink PCI Bridge+ X; H7 Z- T( a* ~
— Security Block6 M5 _: X/ g& [0 Z/ }
■ 0.13 micron process5 e) n7 R0 t. ^1 f/ _1 u
■ Packaging:
2 [! C9 d. u8 M2 M) Q— 481-Terminal BGU (Ball Grid Array Cavity Up) with( m/ Z3 r$ N3 S9 c" d
internal heatspreader. A+ y: b0 W. M W. w
■ Single packaging option supports all features
* O5 b, F* D2 o/ V v7 x1 l0 QCPU Processor Features8 Q: z" ?# q* [4 H- o4 d
■ x86/x87-compatible CPU core2 r% C4 L; ~+ r5 E0 Y+ \" f" v; L4 S
■ Performance:6 ~( @4 d9 v; I8 ]% W
— Processor frequency: up to 500 MHz
8 R$ K5 I; ]- N# p+ b% I+ S— Dhrystone 2.1 MIPs: 150 to 4503 J4 ]* h- b1 B6 X2 P8 z
— Fully pipelined FPU# R0 U7 K0 i& e
■ Split I/D cache/TLB (Translation Look-aside Buffer):
; \% g0 D/ ?* E9 K— 64 KB I-cache/64 KB D-cache5 A' l; N* E5 U0 _
— 128 KB L2 cache configurable as I-cache, D-cache,* t1 o$ N7 r4 U. U7 N4 _
or both3 `+ U5 ?, Q3 c7 y
■ Efficient prefetch and branch prediction
$ U M8 Z; z- ^, F/ J■ Integrated FPU that supports the MMX® and
3 r$ K, S; t$ ?9 u/ PAMD 3DNow!™ instruction sets
: b* N! x# m# c8 a■ Fully pipelined single precision FPU hardware with, M R; \# i' m+ _2 H" R7 ?
microcode support for higher precisions* l* L; m' \! [* I9 T5 M% R# \
GeodeLink™ Control Processor
# h. t9 Y; F+ X: S# ]2 m$ k8 Y& m■ JTAG interface:
+ I# \6 [% P* J' s— ATPG, Full Scan, BIST on all arrays
$ w% C$ C) Z( k g4 q, _— 1149.1 Boundary Scan compliant
6 N* V5 |, o4 @ z, f& U+ r■ ICE (in-circuit emulator) interface
, h9 z' p: @- r5 h■ Reset and clock control2 k" |/ ~: q: g
■ Designed for improved software debug methods and
6 A: f0 T5 X3 G! Zperformance analysis+ a _# c8 v: C# f& q1 Q
■ Power Management:$ @! r; w& e3 m! W( a
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @( V+ U# T1 m. |$ ]! f' M
500 MHz max power
) x1 n6 Y- J8 |6 m( K! E— GeodeLink active hardware power management4 \6 { p% Q3 Q, C! c/ s, [$ y
— Hardware support for standard ACPI software power; Y; F4 B; o. }7 B
management. N; t1 d+ J' m) K
— I/O companion SUSP/SUSPA power controls
# ^5 J( {# c X" T— Lower power I/O& J) y1 }4 z2 ^) [2 M9 u4 e- g, w, k
— Wakeup on SMI/INTR0 @ q( b0 c. a* D3 U2 X. [
■ Designed to work in conjunction with the
" V2 v+ q' z( E& J/ Z! y1 IAMD Geode™ CS5536 companion device- K7 ?4 g$ d; F* L0 V4 T' R
GeodeLink™ Architecture% C, h6 W) g% i2 w5 F% ?* o! k
■ High bandwidth packetized uni-directional bus for
# a4 G6 t1 U0 O6 o$ S7 Ointernal peripherals
. U1 ^ P2 J& M$ a, E■ Standardized protocol to allow variants of products to be& p3 h6 N# ?" B
developed by adding or removing modules8 S ^) a% _) p
■ GeodeLink Control Processor (GLCP) for diagnostics
1 `2 S$ F% _6 yand scan control7 a2 R) u1 M8 B5 s6 G. P
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
4 ?! Z6 d- d* sGeodeLink™ Memory Controller* |% n1 v/ f0 S3 U2 T' S" }. h) z
■ Integrated memory controller for low latency to CPU and
6 H+ I5 y1 U# y3 ]on-chip peripherals# _3 q3 e M$ M8 e8 r! ^+ D2 V
■ 64-bit wide DDR SDRAM bus operating frequency:- A; V) W' J0 y) ~& c9 O9 H/ P3 W: l
— 200 MHz, 400 MT/S
- \; A7 q+ ?/ A/ ^: V4 U5 A8 ^■ Supports unbuffered DDR DIMMS using up to 1 GB
) W! z# {* d. u8 T% ?DRAM technology& j, j1 ]8 R8 j
■ Supports up to 2 DIMMS (16 devices max)4 d- c9 \# f3 \ j9 S$ Y* N
2D Graphics Processor+ v" |! d+ P1 I2 B' v
■ High performance 2D graphics controller/ l0 Z8 V+ N5 ?: w$ T) L/ B+ r7 k
■ Alpha BLT
, Q& S$ a$ V: Y% _) s■ Microsoft® Windows® GDI GUI acceleration:! `( H; D3 f- M" x6 J# U$ `
— Hardware support for all Microsoft RDP codes
% F; i1 { A g) l8 G■ Command buffer interface for asynchronous BLTs
+ B2 @% L/ j* o: ]: v! P- I■ Second pattern channel support: o# U5 ^6 y0 W# v
■ Hardware screen rotation |
|