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AMD Geode LX 800@0.9W處理器
General Features7 B0 v% ? X8 F# {7 ^8 W% ?
■ Functional blocks include:
' p( Z) \( T- I— CPU Core
% c! g4 n6 }4 @8 X% v5 M. u— GeodeLink™ Control Processor6 b, C0 Z1 |! K. s
— GeodeLink Interface Units; y) m4 R8 C6 N7 m3 r E
— GeodeLink Memory Controller! [- g1 s5 t, R
— Graphics Processor( X/ p$ k/ t8 E. A. u
— Display Controller
% U$ ?. U8 q, C& W+ a: Z— Video Processor
9 O+ K( m9 x$ l+ I# n– TFT Controller/Video Output Port* k+ m, R- b! A7 z' d% z F
— Video Input Port
( t2 J1 i% h7 l— GeodeLink PCI Bridge
) W( s! |$ Q/ I— Security Block
" s: X8 W; y& n! ^; h0 b6 ]# d, M& g■ 0.13 micron process
9 S8 [9 M3 g( u, |0 C: c9 ?' P% e■ Packaging:' J& ^% m% F3 p! ~
— 481-Terminal BGU (Ball Grid Array Cavity Up) with6 g4 `, o. z$ Q* m3 b
internal heatspreader
" C) J; P% n8 ?2 j7 i* G$ X) P■ Single packaging option supports all features
0 t: Z* k6 O/ X! w2 n+ JCPU Processor Features6 l9 X& L* d, T$ f) R e
■ x86/x87-compatible CPU core
+ c& X9 N: C+ [7 s1 B■ Performance:6 F5 s. W" R: Q1 l! b5 H6 p6 k- {
— Processor frequency: up to 500 MHz
. K: L0 Z! K- p" G- u7 ^0 F) }— Dhrystone 2.1 MIPs: 150 to 450% S9 ~% g4 u, H& [9 y7 W
— Fully pipelined FPU: V! h, A# J( K0 v! _9 L. k# f. a
■ Split I/D cache/TLB (Translation Look-aside Buffer):
3 Z' ^ c3 @' e4 j5 n; `— 64 KB I-cache/64 KB D-cache1 z# g# c0 P( [. k# ^
— 128 KB L2 cache configurable as I-cache, D-cache,
) }* M4 S5 L4 h% r/ W ^- nor both
. D9 K2 N3 ]3 x9 ^& Z) Q■ Efficient prefetch and branch prediction6 g" A, P% |/ T
■ Integrated FPU that supports the MMX® and
! h: b% e$ D* _4 y0 E( X( N% vAMD 3DNow!™ instruction sets
% }* H! m5 X+ F4 U( h■ Fully pipelined single precision FPU hardware with
, l- n3 E! B* Q( H) Y& C' p& |microcode support for higher precisions
- B+ |: P: x# t Y4 M1 J) D. oGeodeLink™ Control Processor
$ [! H& ]7 J, i9 M$ t+ C7 K# M■ JTAG interface:; s5 n9 J8 a7 w7 k, N( Y
— ATPG, Full Scan, BIST on all arrays
/ F6 {% {: P9 d/ A; X1 H8 \— 1149.1 Boundary Scan compliant; ^! V e- P& n0 C% X! {- h8 f
■ ICE (in-circuit emulator) interface4 V' K2 \& H8 V/ p: V
■ Reset and clock control
3 N9 K' d1 N1 V, z■ Designed for improved software debug methods and
. D' T! H! R" ]! Z& l _performance analysis
& H H. q5 V \% `# D k: E■ Power Management:
" f" f5 B8 G: y- y# K3 V— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
! Z! ~) A9 F; X( g6 L$ u500 MHz max power
: q% c- E7 ~, |- ?9 t! E— GeodeLink active hardware power management
2 a d E* \$ b! v2 \— Hardware support for standard ACPI software power
1 Y; g& ]# _+ I1 u6 d; Jmanagement) X8 {1 ?8 ?! _7 z0 e
— I/O companion SUSP/SUSPA power controls
- w8 V% l* k) Y9 D7 {) A— Lower power I/O2 A/ Q, ~9 q& G* x8 u( O& R
— Wakeup on SMI/INTR- x; H! ^, {7 T, ]$ O
■ Designed to work in conjunction with the# |& V' P, g( e
AMD Geode™ CS5536 companion device
. ~3 t0 a( I# z5 z# {2 _GeodeLink™ Architecture
0 Q; l) m% _9 U: X0 S A■ High bandwidth packetized uni-directional bus for7 \* ?/ g. w& |+ U- v
internal peripherals
% e( l# M- G3 j8 Q3 v: k" G E■ Standardized protocol to allow variants of products to be
5 D: u/ e) Q" g$ {) F+ w fdeveloped by adding or removing modules
@0 U9 l# t& U+ g' O, v■ GeodeLink Control Processor (GLCP) for diagnostics$ q" q9 [0 u2 U; A8 a
and scan control0 u# V3 [0 S/ r- R3 v; y) A
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
% q% a$ a& I# x! m6 EGeodeLink™ Memory Controller
/ n2 C; k6 M, k# b$ D■ Integrated memory controller for low latency to CPU and( w6 _( @* U- z6 w2 T- J6 t
on-chip peripherals1 n5 O0 ^1 `' m% V0 O8 ^
■ 64-bit wide DDR SDRAM bus operating frequency:- n! Q" K, v- O5 w+ s: b
— 200 MHz, 400 MT/S
# ~' m& L: e8 W. C d■ Supports unbuffered DDR DIMMS using up to 1 GB
; J b8 Y" [' T4 C3 ^7 W3 z0 SDRAM technology
/ f5 W2 a- b3 f4 g" F8 I+ W: z3 ?■ Supports up to 2 DIMMS (16 devices max)
- O8 b. K$ c& _4 L2D Graphics Processor$ a4 h6 N- d2 j+ B/ ?1 ?
■ High performance 2D graphics controller
: G: f8 k! j8 i& v! g. {% W■ Alpha BLT
3 P0 A% ?7 O, `' F8 `■ Microsoft® Windows® GDI GUI acceleration:4 t+ O e h' G+ I# T% u1 L
— Hardware support for all Microsoft RDP codes7 C$ _* T* Z- k7 L0 F" U
■ Command buffer interface for asynchronous BLTs$ w+ q7 a' t4 Y; s
■ Second pattern channel support: Z% {$ x. t; G# _4 t: H
■ Hardware screen rotation |
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