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AMD Geode LX 800@0.9W處理器
General Features0 [3 E! o8 v2 `- r" s
■ Functional blocks include:/ \4 C+ s* ?; K. ]. {, v) L- L2 ~% J
— CPU Core' n/ a( u. J# _* v' k3 q
— GeodeLink™ Control Processor5 J- w; E+ B4 P. N$ `, R3 s, f+ \9 T
— GeodeLink Interface Units U' J; a) O B8 @8 z
— GeodeLink Memory Controller- j2 ?, M" D" s: B4 N8 x
— Graphics Processor$ i* O8 f) A5 S% c! V
— Display Controller& e1 h" B7 k6 D9 h, L8 E6 g- d" Y0 U
— Video Processor
$ K$ ?4 ]4 j. V, |– TFT Controller/Video Output Port
9 i3 L. P: |" ^& l& D8 k% V— Video Input Port
- `* n1 u! n6 E" g# h7 N5 l$ @7 |— GeodeLink PCI Bridge
! @" N4 J1 S' S— Security Block; d5 \6 C: H+ h; g1 H$ f5 J. o
■ 0.13 micron process
4 O0 y+ L! d1 G4 W5 ^; \* O- m* F/ T' ~■ Packaging:, Y7 L, G. o: J) R1 k
— 481-Terminal BGU (Ball Grid Array Cavity Up) with5 H' c5 r6 V" z. c! \
internal heatspreader6 n; |% C; A/ Z+ n6 `+ Q* n& L
■ Single packaging option supports all features) o5 R/ a+ g5 y8 r4 V0 p
CPU Processor Features; ~& B( b+ D6 V+ v, o1 q8 G. p
■ x86/x87-compatible CPU core
* I5 T3 T s+ y; F+ T" L■ Performance:* F, J0 ^1 h2 G: ^- p5 F
— Processor frequency: up to 500 MHz3 K7 e4 X; G9 H
— Dhrystone 2.1 MIPs: 150 to 450
# y& Q! H4 N: F— Fully pipelined FPU2 \0 P7 |+ S$ g% H( F
■ Split I/D cache/TLB (Translation Look-aside Buffer):
* F, o: x9 M& K% h; C3 U3 Y— 64 KB I-cache/64 KB D-cache
1 D. ~0 x( [* }— 128 KB L2 cache configurable as I-cache, D-cache,
9 i; ~) A6 y [' o7 [or both
' V8 y) b! P4 B% t7 `4 ~■ Efficient prefetch and branch prediction
1 u: L1 G0 `% d F y- ?0 z■ Integrated FPU that supports the MMX® and+ {, F, t1 K+ U
AMD 3DNow!™ instruction sets
; Z9 t# _4 Z7 r. o m■ Fully pipelined single precision FPU hardware with
5 C s, G' f/ _+ k9 b! emicrocode support for higher precisions' P* E& e$ ]1 o/ d" [& G1 l8 f
GeodeLink™ Control Processor g: ]& Y- h, l
■ JTAG interface:
, v7 Q3 ]/ P5 J5 P+ Q6 [* {3 z/ q— ATPG, Full Scan, BIST on all arrays0 j4 B4 `: t% q |+ z( u; |
— 1149.1 Boundary Scan compliant$ ]9 J" J. z, _- a
■ ICE (in-circuit emulator) interface
' s1 q, u. |* V7 ~1 {5 p0 J% e■ Reset and clock control: ^) c$ V& B" n |! V. i
■ Designed for improved software debug methods and
/ m: Q* \. C8 F* eperformance analysis: H+ L( n* _5 f4 H/ ~! A& ^0 C
■ Power Management:
2 G5 V8 Y! A2 D! r— Total Dissipated Power (TDP) 3.8W, 1.6W typical @% Z# h; n1 Q. s8 \& V
500 MHz max power
" \/ d( a K3 v" l$ p$ G— GeodeLink active hardware power management2 d, M: h4 G( k' W# r
— Hardware support for standard ACPI software power
" [; [. y- C/ p& Q. r7 C, e6 R6 {# amanagement7 k7 P3 a& r1 @! t: L
— I/O companion SUSP/SUSPA power controls+ _- E S, f% ^
— Lower power I/O9 i4 Q! Z5 v- M0 H3 p+ l+ d ]
— Wakeup on SMI/INTR
+ p4 c4 U. a: Y7 X3 e% `; V1 J■ Designed to work in conjunction with the- N7 ~. c# O# p# ?
AMD Geode™ CS5536 companion device8 r7 o- T- i) A8 m( e( p( R" d
GeodeLink™ Architecture! R4 S; K4 B# p4 \8 a8 U4 h
■ High bandwidth packetized uni-directional bus for
) E) ^! q0 u F* J' g& ~/ O finternal peripherals
4 {! U K7 ]9 X; O9 H3 x■ Standardized protocol to allow variants of products to be& [' }% V- ]+ U8 h, f; x
developed by adding or removing modules
" a) i* c7 o5 m& s" S( A0 Q■ GeodeLink Control Processor (GLCP) for diagnostics
/ a0 e- D0 w `; ] k/ eand scan control$ H1 w1 k; f7 E# R6 U2 S
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
$ s, ^4 O2 X+ @$ ~GeodeLink™ Memory Controller; X! o5 y' B c* D
■ Integrated memory controller for low latency to CPU and) d" G9 O8 w) Q$ O# O) u
on-chip peripherals
, n6 {$ K2 c* M! x2 ^4 J/ \■ 64-bit wide DDR SDRAM bus operating frequency:
8 S: f3 ^1 ]" h$ p, {— 200 MHz, 400 MT/S
2 G" ~+ v! }% K2 z7 B9 S' e■ Supports unbuffered DDR DIMMS using up to 1 GB7 E1 w/ b$ L: e: S) c
DRAM technology
1 g. B1 w' M; j" ]; j7 Y■ Supports up to 2 DIMMS (16 devices max)& W) X1 `1 e0 J2 W I. E0 M1 x
2D Graphics Processor
! U; F6 |) ]! V; C+ g■ High performance 2D graphics controller# Q% b" Y2 \ {1 s& d+ _
■ Alpha BLT
: w5 z/ c" n* i* w& ~■ Microsoft® Windows® GDI GUI acceleration:
5 ^9 e% q2 H8 L: p/ x U" }1 [— Hardware support for all Microsoft RDP codes
9 S5 D0 I8 |7 ?. J1 P+ u■ Command buffer interface for asynchronous BLTs
5 @6 j' e+ a5 e0 G5 G0 I" y3 E■ Second pattern channel support* ^; x0 z: F9 M( [
■ Hardware screen rotation |
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