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AMD Geode LX 800@0.9W處理器
General Features$ ?8 ~9 O) E6 t! p
■ Functional blocks include:
: u j" D6 P" b— CPU Core
- W% a1 S6 a, L! p0 K— GeodeLink™ Control Processor
0 N* w& `! G4 \9 l9 c# c— GeodeLink Interface Units
& S' K; A; q( Y8 r( z— GeodeLink Memory Controller' ?- t/ O) o* R# G
— Graphics Processor" a# D4 J# _) I9 @; r) l3 N1 _
— Display Controller+ w! X8 \$ q V5 b9 w* C' b
— Video Processor
4 @% z+ R* b( l' I# m– TFT Controller/Video Output Port
' o9 P @1 C6 Z( O. _— Video Input Port
- D# m% A8 z F; O- t— GeodeLink PCI Bridge: k' B! o9 z! ] p; Y
— Security Block
) k5 u1 @9 m- ?* K l7 j4 L, B■ 0.13 micron process) ~- c8 P3 q; ^* g) W& H
■ Packaging:) `& @4 `* [ m
— 481-Terminal BGU (Ball Grid Array Cavity Up) with& V: E9 M1 I! F7 K
internal heatspreader
1 g; O4 |8 `& F" t* v■ Single packaging option supports all features
* l* f% ~4 n3 s: g& wCPU Processor Features
W9 m0 R( t0 `+ r q2 V' E■ x86/x87-compatible CPU core
3 Z8 o) y; a: ]& s' S■ Performance:& V9 \. G g5 K7 V, V# k
— Processor frequency: up to 500 MHz5 `4 {& h- X! y1 M
— Dhrystone 2.1 MIPs: 150 to 450
E3 B8 H! ^( k, O+ b, ]/ k— Fully pipelined FPU
" }; O9 ^) i9 |& E9 A: y+ Q7 q■ Split I/D cache/TLB (Translation Look-aside Buffer):
; z* ]+ w; a) r1 J; C* B— 64 KB I-cache/64 KB D-cache
0 O4 L. |4 r3 X% M5 G9 a— 128 KB L2 cache configurable as I-cache, D-cache,
! \+ [( k( a! v' q+ v vor both- T5 s5 B J5 e1 _- e# j9 G
■ Efficient prefetch and branch prediction
0 R5 a. S, W; N5 _3 F3 g7 r: i5 @8 o■ Integrated FPU that supports the MMX® and
1 Y# o; q( h2 P# t- B7 wAMD 3DNow!™ instruction sets
& a/ } K' Y$ W4 M' k2 j. ~; c% f■ Fully pipelined single precision FPU hardware with
, h9 ?8 {- k/ V4 E' {! J! Vmicrocode support for higher precisions1 \9 a; }! q# c& m/ N
GeodeLink™ Control Processor
7 |" `+ E" i1 F2 N. J■ JTAG interface:
* G1 ^8 K, n/ Y& T— ATPG, Full Scan, BIST on all arrays& h3 ~; x1 o( b$ F
— 1149.1 Boundary Scan compliant
8 i0 o/ Y8 [, [; u& j1 ]( C■ ICE (in-circuit emulator) interface
% k; ^1 ?; z4 j4 o■ Reset and clock control F$ Z* K/ H. S6 z" n# A. e
■ Designed for improved software debug methods and
7 ^2 j) A7 a5 A6 y8 G/ u8 A8 Tperformance analysis
" f( C" G) k8 X: y■ Power Management:
2 {$ g, i) W6 X2 x, o! f7 A9 E6 w— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
6 C2 P! ` o) ?, }2 j# i& \500 MHz max power
0 g7 \7 @. a# M) s+ v0 G0 r— GeodeLink active hardware power management
5 d0 q1 l0 |% P/ ]* i— Hardware support for standard ACPI software power
( S5 j* {; z1 E, p3 Pmanagement
* q/ S9 W8 u& Z3 t/ x0 t, L+ a— I/O companion SUSP/SUSPA power controls9 d( J: \! l, r5 j
— Lower power I/O
4 W* q3 l% m% q7 g* [/ G— Wakeup on SMI/INTR
1 A" b& B8 ^7 o- F+ C. f6 P■ Designed to work in conjunction with the; ~$ o; s$ L4 G2 b: N: U, Q4 q
AMD Geode™ CS5536 companion device
+ c2 s1 e2 b4 N8 a( \GeodeLink™ Architecture
/ j8 `1 D2 c- M■ High bandwidth packetized uni-directional bus for3 }4 j5 b0 ], q2 u1 S
internal peripherals
3 l- L+ `! K6 h% l■ Standardized protocol to allow variants of products to be
3 a) D7 ]9 e' [; {5 gdeveloped by adding or removing modules
8 E6 x" q* x% `3 z■ GeodeLink Control Processor (GLCP) for diagnostics
' c& F B/ b4 y: U4 Gand scan control
6 C: C2 E, U2 Q% R: c■ Dual GeodeLink Interface Units (GLIUs) for device interconnect' R; V: W$ H- T6 j6 C
GeodeLink™ Memory Controller' N; s* A9 D% s1 w
■ Integrated memory controller for low latency to CPU and" w8 K+ q* x2 Q
on-chip peripherals
7 v3 u0 U* N+ u! m# m; t# [4 L■ 64-bit wide DDR SDRAM bus operating frequency:
$ t7 F m( j" m( O5 D& y( ~— 200 MHz, 400 MT/S
* W+ J7 \( n# d7 P■ Supports unbuffered DDR DIMMS using up to 1 GB
" V- L) x1 P; V+ d, Q4 n8 N# ~DRAM technology' B# `5 N* d$ Y0 @2 `
■ Supports up to 2 DIMMS (16 devices max)
! n: N$ o" \, L3 D" G" {. p2D Graphics Processor
% C/ L- V5 A5 z8 i■ High performance 2D graphics controller
! A8 d& f4 o) R+ p& e( E% o; m■ Alpha BLT
; p0 k7 v0 h, g. M) M, M( P7 T3 g■ Microsoft® Windows® GDI GUI acceleration:
. _; m2 m% X; J) i) R— Hardware support for all Microsoft RDP codes; ^) s/ _! N8 p
■ Command buffer interface for asynchronous BLTs
( G/ ~& v2 r- r+ w, a■ Second pattern channel support
5 F, E, h7 l2 g■ Hardware screen rotation |
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