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Layout Guidelines for Optimized ESD Protection Diodes% S, o/ B4 L$ h% y
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Karan Bhatia and Elyse Rosenbaum
/ x: P; |( t! o$ SDepartment of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign7 ?' M& N$ J. l/ L& o
1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu1 Y s( H2 S3 A S4 u
9 a L) V7 o8 ZAbstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are0 C5 s' ?0 e$ N+ h9 I2 r6 H* m
investigated. The current compression point (ICP) is introduced to define the maximum current handling2 i h& L4 }$ @# K; ~# s) Q$ `, U
capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the0 K5 `/ I5 U* W; o; I) D
performance of the structures investigated herein. |
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